Schematic asus k52n rev1.0 schematic

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asus k52n rev1.0 schematic

asus k52n=1=rev1.0.pdf




Technical Specifications

ParameterValue
BrandASUSTeK COMPUTER INC.
ModelK52N
Project CodeNB 1.1.0
Board NumberK52N
RevisionB
DateMonday, February 08, 2010
CPU PlatformGriffin
EngineerVincent_Chiang
Sheet TitleGriffin HT I/F

Technical Summary

This is an ASUSTeK Computer Inc. motherboard schematic for the K52N model, project code NB 1.1.0, revision B, dated Monday, February 08, 2010. The CPU platform is identified as Griffin, with the sheet dedicated to the Griffin HT I/F (HyperTransport Interface). The engineer assigned to this design is Vincent_Chiang. The schematic details the HyperTransport link connections between the CPU socket (BGA638_50_26SQ_S1G2_OEM) and the system, including differential signal pairs for data, clock, and control lines. The document provides specific component values for decoupling capacitors on the VLDT power rail, including 10µF/6.3V and 0.1µF/16V capacitors, as well as 180pF/50V capacitors. A layout note indicates that if VLDT is connected only on one side, a 4.7µF capacitor should be added to the island side.

Technician FAQ

Q: What is the board number and revision for this ASUSTeK motherboard?

A: The board number is K52N, revision B.

Q: What CPU platform is used on this motherboard?

A: The CPU platform is Griffin.

Q: What is the date of this schematic?

A: The schematic is dated Monday, February 08, 2010.

Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
 

Attachments

  • Asus K52N=1=Rev1.0.zip
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