dell latitude xt tablet pc e5400 parker mb 4s701 06240-sc x01 0322 rev-sc 1
Technical Specifications
Technical Summary
This Wistron Parker SC reference design, documented under number A3153 and dated March 22, 2007, is built around an Intel Yonah or Merom ULV mobile CPU with a 533MHz FSB, paired with an ATI SB600 southbridge. The system utilizes dual-channel DDR2 533/667MHz memory via a single 200-pin SODIMM socket. The embedded controller is an SMSC MEC5025, programmable via SPI, and the BIOS is stored on a 2MB SPI flash IC. Power management is handled by a combination of ISL6236/MAX8778, ADP3207, TPS51100, and MAX8794 regulators, with an ISL88731 battery charger. Audio is provided by a STAC 9205 Azalia codec, networking by a BCM5756ME Gigabit LAN controller, and thermal monitoring by an EMC4001 sensor. A TI 7402 card reader is also integrated into the platform.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is an SMSC MEC5025, programmable via SPI.
Q: What is the BIOS flash configuration?
A: The BIOS is stored on a 2MB SPI flash IC.
Q: What charging IC is used?
A: The battery charger IC is an ISL88731.
Q: What is the memory architecture?
A: The board supports dual-channel DDR2 533/667MHz memory via a single 200-pin SODIMM socket.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Wistron Corporation |
| Project Code | 91.4S701.001 |
| Board Number | 48.4S701.0SC |
| Revision | 06240-SC |
| Date | Thursday, March 22, 2007 |
| Document Number | A3153 |
| CPU Platform | Intel Mobile CPU |
| CPU Model | Yonah / Merom ULV |
| PCH / Southbridge | ATI SB600 |
| EC / KBC | SMSC MEC5025 |
| EC/KBC Programmable | SPI |
| Audio Codec | STAC 9205 |
| BIOS / SPI Flash | SPI FLASH 2MB |
| Charging IC | ISL88731 |
| Power IC(s) | ISL6236/MAX8778, ADP3207, TPS51100, MAX8794 |
| RAM Type | DDRII 533/667MHz |
| RAM Architecture | Dual DDR2 Channel |
| RAM Quantity / Slots | 200-PIN DDR2 SODIMM |
| LAN IC | BCM5756ME |
| Card Reader IC | TI 7402 |
| Thermal Sensor | EMC4001 |
Technical Summary
This Wistron Parker SC reference design, documented under number A3153 and dated March 22, 2007, is built around an Intel Yonah or Merom ULV mobile CPU with a 533MHz FSB, paired with an ATI SB600 southbridge. The system utilizes dual-channel DDR2 533/667MHz memory via a single 200-pin SODIMM socket. The embedded controller is an SMSC MEC5025, programmable via SPI, and the BIOS is stored on a 2MB SPI flash IC. Power management is handled by a combination of ISL6236/MAX8778, ADP3207, TPS51100, and MAX8794 regulators, with an ISL88731 battery charger. Audio is provided by a STAC 9205 Azalia codec, networking by a BCM5756ME Gigabit LAN controller, and thermal monitoring by an EMC4001 sensor. A TI 7402 card reader is also integrated into the platform.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is an SMSC MEC5025, programmable via SPI.
Q: What is the BIOS flash configuration?
A: The BIOS is stored on a 2MB SPI flash IC.
Q: What charging IC is used?
A: The battery charger IC is an ISL88731.
Q: What is the memory architecture?
A: The board supports dual-channel DDR2 533/667MHz memory via a single 200-pin SODIMM socket.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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