hp g60 astrosphere_amd 07241-3 schematic
hp g60=1=astrosphere_amd 07241-3.pdf
Technical Specifications
Technical Summary
The Wistron Astrosphere SA motherboard (Document Number A3144, dated March 5, 2009) is built around an AMD CPU NPT Processor Rev. G1 in an S1G2 package, paired with an nVIDIA MCP77 southbridge. System memory consists of two DDRII 667/800 slots configured as Channel A Slot 0 and Channel B Slot 1. The embedded controller is a WPCE773L, and the audio subsystem is handled by a CX20561-14Z CX20548-11Z HD audio codec. Power management is provided by an ISL6265 CPU core regulator, TPS51125 and TPS51116 system DC/DC converters, SC412A and SC471A regulators, and an APL5913 LDO. Charging is managed by a MAX8731AETI charger accepting DCBATOUT at 18V 3.0A. Networking includes an RTL8201N 10/100 LAN controller and a Mini Card 802.11a/b/g wireless module. Storage connectivity is supported by an RTS5158 card reader, and USB expansion is handled by a G7921MB hub.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is a WPCE773L.
Q: What charging IC and architecture are used?
A: The charger is a MAX8731AETI from Maxim, accepting DCBATOUT at 18V 3.0A and 5V 100mA.
Q: What memory configuration does this board support?
A: The board supports DDRII 667/800 memory across two slots, configured as Channel A Slot 0 and Channel B Slot 1.
Q: What power management ICs are present?
A: Power management ICs include ISL6265 for CPU core, TPS51125 and TPS51116 for system DC/DC, SC412A and SC471A for additional rails, and APL5913 for LDO regulation.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
hp g60=1=astrosphere_amd 07241-3.pdf
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Wistron Corporation |
| Project Code | Astrosphere SA |
| Document Number | A3144 |
| Date | Thursday, March 05, 2009 |
| CPU Platform | AMD CPU NPT Processor Rev. G1 S1G2 package |
| PCH / Southbridge | nVIDIA MCP77 |
| EC / KBC | WPCE773L |
| Audio Codec | CX20561-14Z CX20548-11Z HD AUDIO CODEC |
| Charging IC | MAX8731AETI |
| Charger Architecture | MAXIM CHARGER MAX8731AETI INPUTS DCBATOUT BT+ 18V 3.0A 5V 100mA |
| Power IC(s) | ISL6265, TPS51125, TPS51116, SC412A, SC471A, APL5913 |
| RAM Type | DDRII 667/800 |
| RAM Architecture | DDRII Channel A Slot 0, DDRII Channel B Slot 1 |
| RAM Quantity / Slots | 2 |
| LAN IC | RTL8201N |
| WiFi / WLAN IC | Mini Card 802.11a/b/g |
| Card Reader IC | RTS5158 |
| USB Hub IC | G7921MB |
Technical Summary
The Wistron Astrosphere SA motherboard (Document Number A3144, dated March 5, 2009) is built around an AMD CPU NPT Processor Rev. G1 in an S1G2 package, paired with an nVIDIA MCP77 southbridge. System memory consists of two DDRII 667/800 slots configured as Channel A Slot 0 and Channel B Slot 1. The embedded controller is a WPCE773L, and the audio subsystem is handled by a CX20561-14Z CX20548-11Z HD audio codec. Power management is provided by an ISL6265 CPU core regulator, TPS51125 and TPS51116 system DC/DC converters, SC412A and SC471A regulators, and an APL5913 LDO. Charging is managed by a MAX8731AETI charger accepting DCBATOUT at 18V 3.0A. Networking includes an RTL8201N 10/100 LAN controller and a Mini Card 802.11a/b/g wireless module. Storage connectivity is supported by an RTS5158 card reader, and USB expansion is handled by a G7921MB hub.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is a WPCE773L.
Q: What charging IC and architecture are used?
A: The charger is a MAX8731AETI from Maxim, accepting DCBATOUT at 18V 3.0A and 5V 100mA.
Q: What memory configuration does this board support?
A: The board supports DDRII 667/800 memory across two slots, configured as Channel A Slot 0 and Channel B Slot 1.
Q: What power management ICs are present?
A: Power management ICs include ISL6265 for CPU core, TPS51125 and TPS51116 for system DC/DC, SC412A and SC471A for additional rails, and APL5913 for LDO regulation.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Attachments
Last edited:
