hp pavilion dv6 quanta lx3-lx5_huror river_rev1a schematic
hp pavilion dv6=1=quanta lx3-lx5_huror river_rev1a.pdf
Technical Specifications
Technical Summary
This Compal LA-517 Rev 1A motherboard, dated October 1, 2010, is designed for the Intel Sandy Bridge CPU platform using an rPGA 989 socket. The system is built around a Platform Controller Hub (PCH) and supports dual graphics configurations with either an ATI Robson M2 or ATI Capliano Pro GPU. The embedded controller is a KB3926 D2, and the audio codec is an ALC269. System memory consists of two DDR3-SODIMM slots supporting DDR3 1066/1333 MT/s. The charging architecture is managed by a P2806 system charger, with power regulation handled by multiple ICs including the ADP3212 for CPU core, RT8204, RT8206B, RT8207G, RT8208, RT9018A, and VT358. Networking is provided by a Realtek RTL8111(E) Gigabit LAN controller and a Shirley Peak wireless module. The board also features a Realtek RTS5138 card reader, a 9LRS3197 clock generator, a VRC5333 touchscreen controller, and a JR524F accelerometer.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is a KB3926 D2.
Q: What charging IC and architecture does this board use?
A: The system charger is a P2806 IC.
Q: What are the power management ICs on this motherboard?
A: Power regulation ICs include ADP3212 (CPU core), RT8204, RT8206B, RT8207G, RT8208, RT9018A, and VT358.
Q: What graphics configurations are supported?
A: The board supports ATI Robson M2 (128bit) or ATI Capliano Pro (128bit) GPUs.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
hp pavilion dv6=1=quanta lx3-lx5_huror river_rev1a.pdf
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Compal |
| Project Code | LA-517 |
| Board Number | LA-517 |
| Revision | 1A |
| Date | Friday, October 01, 2010 |
| CPU Platform | Intel Sandy (rPGA 989) |
| PCH / Southbridge | Platform Controller Hub PCH 3.5Watt |
| GPU Type | ATI Robson M2 (128bit) / ATI Capliano Pro (128bit) |
| EC / KBC | KB3926 D2 |
| Audio Codec | ALC269 |
| BIOS / SPI Flash | System BIOS |
| Charging IC | P2806 |
| Charger Architecture | System Charger (P2806) |
| Power IC(s) | RT8204, RT8206B, RT8208, RT9018A, VT358, RT8207G, ADP3212 |
| RAM Type | DDR3 |
| RAM Architecture | DDR3-SODIMM |
| RAM Quantity / Slots | 2 |
| Card Reader IC | Realtek RTS5138 |
| LAN IC | Realtek RTL8111(E) |
| WiFi / WLAN IC | Shirley Peak 802.11a/b/g/n |
| Clock Generator | 9LRS3197 |
| Touchscreen Controller | VRC5333 |
| Accelerometer | JR524F |
| Document Number | 1122334455667788AABBCCDD |
Technical Summary
This Compal LA-517 Rev 1A motherboard, dated October 1, 2010, is designed for the Intel Sandy Bridge CPU platform using an rPGA 989 socket. The system is built around a Platform Controller Hub (PCH) and supports dual graphics configurations with either an ATI Robson M2 or ATI Capliano Pro GPU. The embedded controller is a KB3926 D2, and the audio codec is an ALC269. System memory consists of two DDR3-SODIMM slots supporting DDR3 1066/1333 MT/s. The charging architecture is managed by a P2806 system charger, with power regulation handled by multiple ICs including the ADP3212 for CPU core, RT8204, RT8206B, RT8207G, RT8208, RT9018A, and VT358. Networking is provided by a Realtek RTL8111(E) Gigabit LAN controller and a Shirley Peak wireless module. The board also features a Realtek RTS5138 card reader, a 9LRS3197 clock generator, a VRC5333 touchscreen controller, and a JR524F accelerometer.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is a KB3926 D2.
Q: What charging IC and architecture does this board use?
A: The system charger is a P2806 IC.
Q: What are the power management ICs on this motherboard?
A: Power regulation ICs include ADP3212 (CPU core), RT8204, RT8206B, RT8207G, RT8208, RT9018A, and VT358.
Q: What graphics configurations are supported?
A: The board supports ATI Robson M2 (128bit) or ATI Capliano Pro (128bit) GPUs.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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