Schematic iphone 5s 051-9478 820-3292-a schematic

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iphone 5s 051-9478_820-3292-a schematic

iphone 5s=1=051-9478_820-3292-a.pdf




Technical Specifications

ParameterValue
CPU PlatformH6P
BasebandPOP-1GB—DDRSC58960X01-AO30
JTAG InterfaceTRISTARBIAPJTAGSWDIO, TRISTARTOAPJTAGSWCLK
HSIC InterfaceHSIC0_DATA, HSIC0_STB, HSIC1_DATA, HSIC1_STB, HSIC2_DATA, HSIC2_STB
USB InterfaceTRISTARUSB0, TRISTARUSB1
XTAL Frequency24.000MHZ-30PPM-9.5PF-60OHM
USB_REXT Value200
Board ReferenceH6P

Technical Summary

The H6P platform integrates a POP-1GB DDR SDRAM baseband module identified as SC58960X01-AO30. The JTAG interface is routed through TRISTARBIAPJTAGSWDIO and TRISTARTOAPJTAGSWCLK signals. Three HSIC interfaces are present: HSIC0, HSIC1, and HSIC2, each with DATA and STB lines. Two TRISTAR USB interfaces, TRISTARUSB0 and TRISTARUSB1, are configured. The reference crystal is a 24.000 MHz unit with 30 PPM tolerance and 9.5 pF load capacitance. The USB_REXT resistor value is specified as 200 ohms for the H6P revision, replacing the previous 44.2 ohm value used on the H5 platform. The board reference designator is H6P.

Technician FAQ

Q: What is the baseband module used on this H6P platform?

A: The baseband module is a POP-1GB DDR SDRAM identified as SC58960X01-AO30.

Q: What is the USB_REXT resistor value for the H6P platform?

A: The USB_REXT resistor value is 200 ohms, replacing the previous 44.2 ohm value used on the H5 platform.

Q: What JTAG interfaces are present on this board?

A: The JTAG interfaces are TRISTARBIAPJTAGSWDIO and TRISTARTOAPJTAGSWCLK.

Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
 

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