Salim Badakhshan
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Lenovo Miix 300-10IBY M1015BFP-MB Ver 1.3 ANZHEN4 MRD8 P1 Schematic
Technical Specifications
Technical Summary
This Intel Corporation reference design, project code ANZHEN4_MRD8_P1, revision 1P0, dated March 21, 2014, is built around the SSGN+V2P8A CPU platform. The board number is H38551-200 / H38552-002, with document number 87541DDCB87CAA62B334. The design incorporates SPI NOR Flash for BIOS storage, an audio codec, and a battery and debug connector for charging and debug functions. Memory architecture supports DDR VREF with memory devices 0 and 1. Peripheral connectivity includes a micro-SD connector, HDMI level shifters, and a WIFI-BT module. Power management is handled by a comprehensive PMIC subsystem comprising switching regulators, LDOs, external regulators, and host/misc interfaces. The board also includes front and rear cameras, a touch controller, and display backlight and bias voltage regulators.
Technician FAQ
Q: What is the project code and board number for this Intel reference design?
A: The project code is ANZHEN4_MRD8_P1, revision 1P0, with board numbers H38551-200 and H38552-002.
Q: What type of BIOS flash is used on this motherboard?
A: The design uses SPI NOR Flash for BIOS storage.
Q: What is the memory architecture of this board?
A: The board supports DDR VREF with memory devices 0 and 1.
Q: What power management ICs are present on this board?
A: The PMIC subsystem includes switching regulators (BUCK 1-6), LDOs (DLDO 1-3, ELDO 1-3, FLDO 1-2, ALDO 1-3, GPLDO 0-1), and external regulators.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Intel |
| Motherboard Manufacturer | Intel Corporation |
| Project Code | ANZHEN4_MRD8_P1 |
| Board Number | H38551-200 / H38552-002 |
| Revision | 1P0 |
| Date | Fri Mar 21 10:49:01 2014 |
| Document Number | 87541DDCB87CAA62B334 |
| CPU Platform | SSGN+V2P8A |
| Audio Codec | AUDIO CODEC |
| BIOS / SPI Flash | SPI NOR FLASH |
| Charging IC | BATTERY & DEBUG CONNECTOR |
| RAM Type | DDR VREF |
| RAM Architecture | MEMORY DEVICE 0 & 1 |
| Card Reader IC | MICRO-SD CONNECTOR |
| HDMI Level Shifter | HDMI LEVEL SHIFTERS |
| WiFi / WLAN IC | WIFI-BT |
| PMIC | PMIC: SWITCHING REGULATORS / PMIC: LDOS / PMIC: EXTERNAL REGULATORS / PMIC: HOST & MISC INTERFACES |
Technical Summary
This Intel Corporation reference design, project code ANZHEN4_MRD8_P1, revision 1P0, dated March 21, 2014, is built around the SSGN+V2P8A CPU platform. The board number is H38551-200 / H38552-002, with document number 87541DDCB87CAA62B334. The design incorporates SPI NOR Flash for BIOS storage, an audio codec, and a battery and debug connector for charging and debug functions. Memory architecture supports DDR VREF with memory devices 0 and 1. Peripheral connectivity includes a micro-SD connector, HDMI level shifters, and a WIFI-BT module. Power management is handled by a comprehensive PMIC subsystem comprising switching regulators, LDOs, external regulators, and host/misc interfaces. The board also includes front and rear cameras, a touch controller, and display backlight and bias voltage regulators.
Technician FAQ
Q: What is the project code and board number for this Intel reference design?
A: The project code is ANZHEN4_MRD8_P1, revision 1P0, with board numbers H38551-200 and H38552-002.
Q: What type of BIOS flash is used on this motherboard?
A: The design uses SPI NOR Flash for BIOS storage.
Q: What is the memory architecture of this board?
A: The board supports DDR VREF with memory devices 0 and 1.
Q: What power management ICs are present on this board?
A: The PMIC subsystem includes switching regulators (BUCK 1-6), LDOs (DLDO 1-3, ELDO 1-3, FLDO 1-2, ALDO 1-3, GPLDO 0-1), and external regulators.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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