Salim Badakhshan
Registered
Lenovo Thinkpad L13 GEN2- LAR-2 MB 19837-1 Schematic
Technical Specifications
Technical Summary
The Wistron ARES-2 (LAR-2) motherboard, project code 4PD0LL010001, board number 19837-1, is built around the Intel Tigerlake-UP3 platform. The system utilizes integrated Intel Tigerlake-U Series graphics and features dual-channel DDR4 memory down architecture. The embedded controller is an NPCE68AP, and the audio codec is a RealTek ALC3287. The board employs a BQ25710ARSNR battery charger/selector and a multi-rail power delivery system using NCP302045LMNTWG, NCP81253MNTBG, NCP81218MNTXG, TPS51393RJER, TPS51395RJER, TPS51396RJER, TPS51486RJER, and RT5797ALGQW regulators. Networking is provided by an Intel 219LM/VI GbE PHY, with wireless connectivity via Jefferson Peak or Harrison Peak CNVi modules. The BIOS is stored on both 16MB and 32MB SPI flash ICs. A RealTek RTS5232S-GR manages the card reader interface.
Technician FAQ
Q: What is the embedded controller (EC/KBC) used on this motherboard?
A: The embedded controller is an NPCE68AP.
Q: What BIOS flash configurations are present?
A: The board uses both a 16MB SPI Flash and a 32MB SPI Flash.
Q: What is the charging IC and architecture?
A: The charging IC is a BQ25710ARSNR, configured as a battery charger/selector.
Q: What is the memory type and architecture?
A: The memory is DDR4 with a MEMORY DOWN architecture.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Wistron Corporation |
| Model | ARES-2 (LAR-2) |
| Motherboard Manufacturer | Wistron Corporation |
| Project Code | 4PD0LL010001 |
| Board Number | 19837-1 |
| Revision | LAR-2 |
| Date | 2020-08-01 |
| CPU Platform | Tigerlake-UP3 |
| EC / KBC | NPCE68AP |
| Audio Codec | RealTek ALC3287 |
| BIOS / SPI Flash | SPI Flash 16MB, SPI Flash 32MB |
| Charging IC | BQ25710ARSNR |
| Charger Architecture | Battery Charger/Selector |
| Power IC(s) | NCP302045LMNTWG, NCP81253MNTBG, NCP81218MNTXG, TPS51393RJER, TPS51395RJER, TPS51396RJER, TPS51486RJER, RT5797ALGQW |
| RAM Type | DDR4 |
| RAM Architecture | MEMORY DOWN |
| LAN IC | Intel 219LM/VI |
| WiFi / WLAN IC | Jefferson Peak, Harrison Peak |
| Card Reader IC | RTS5232S-GR |
| GPU Type | Intel Tigerlake-U Series |
| Graphics Architecture | Integrated |
| Document Number | A41106 |
Technical Summary
The Wistron ARES-2 (LAR-2) motherboard, project code 4PD0LL010001, board number 19837-1, is built around the Intel Tigerlake-UP3 platform. The system utilizes integrated Intel Tigerlake-U Series graphics and features dual-channel DDR4 memory down architecture. The embedded controller is an NPCE68AP, and the audio codec is a RealTek ALC3287. The board employs a BQ25710ARSNR battery charger/selector and a multi-rail power delivery system using NCP302045LMNTWG, NCP81253MNTBG, NCP81218MNTXG, TPS51393RJER, TPS51395RJER, TPS51396RJER, TPS51486RJER, and RT5797ALGQW regulators. Networking is provided by an Intel 219LM/VI GbE PHY, with wireless connectivity via Jefferson Peak or Harrison Peak CNVi modules. The BIOS is stored on both 16MB and 32MB SPI flash ICs. A RealTek RTS5232S-GR manages the card reader interface.
Technician FAQ
Q: What is the embedded controller (EC/KBC) used on this motherboard?
A: The embedded controller is an NPCE68AP.
Q: What BIOS flash configurations are present?
A: The board uses both a 16MB SPI Flash and a 32MB SPI Flash.
Q: What is the charging IC and architecture?
A: The charging IC is a BQ25710ARSNR, configured as a battery charger/selector.
Q: What is the memory type and architecture?
A: The memory is DDR4 with a MEMORY DOWN architecture.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Attachments
Last edited by a moderator:
