Lenovo Thinkpad T14-T15-P43s-P53s Gen2 NM-D351 Rev 1.0 Schematic
Technical Specifications
Technical Summary
This Lenovo T14/T15/P43s/P53s Gen2 LCFC NM-D351 Rev 1.0 schematic details an Intel Tiger Lake U platform with DDR4 SUB memory architecture supporting two SODIMM slots. The embedded controller is a MEC1503H-L1-I/3Y-TR BGA, with a dedicated W25Q80EWSNIGT EC flash ROM. The main BIOS SPI flash is a W25Q80DVUXIET with a total capacity of 32MB. Graphics are handled by an nVidia N18S-LP QN20-M dGPU. The charging IC is a BQ4179MWV-E2 in a WQFN56 package, and power delivery is managed by a TI TPS65994-AD controller. Audio is provided by an ALC3287-CG codec in a MQFN48 package. Connectivity includes an Intel GbE PHY Jacksonville I219 LAN IC, an Intel AX201PD2WGQ WiFi/WLAN module, and a Parade-PS8409A HDMI re-timer. The card reader is a Realtek RTS5232S-GR multimedia controller.
Technician FAQ
Q: What BIOS IC model is used on this motherboard?
A: The main BIOS SPI flash is a W25Q80DVUXIET with a total capacity of 32MB.
Q: What EC/KBC chip is used and is it programmable?
A: The embedded controller is a MEC1503H-L1-I/3Y-TR BGA. The schematic shows a dedicated W25Q80EWSNIGT SPI flash for the EC firmware, indicating the EC is programmable via its external flash.
Q: What is the charging IC and power architecture?
A: The charging IC is a BQ4179MWV-E2 in a WQFN56_7X7 package. Power delivery is managed by a TI TPS65994-AD PD controller.
Q: What is the memory configuration?
A: The board uses DDR4 SUB memory architecture with two SODIMM slots supporting up to DDR4 4266MHz.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Lenovo |
| Model | T14/T15/P43s/P53s Gen2 |
| Motherboard Manufacturer | LCFC |
| Project Code | HT4B0/HP4B0/HT5B1/HP5B1/HT4B2 |
| Board Number | NM-D351 |
| Revision | 1.0 |
| Date | Friday, December 04, 2020 |
| CPU Platform | Intel Tiger Lake U |
| GPU Type | nVidia N18S-LP QN20-M |
| EC / KBC | MEC1503H-L1-I/3Y-TR BGA |
| Audio Codec | ALC3287-CG_MQFN48 |
| BIOS / SPI Flash | W25Q80DVUXIET |
| BIOS Flash Capacity | 32MB |
| EC Flash / ROM | W25Q80EWSNIGT |
| Charging IC | BQ4179MWV-E2_WQFN56_7X7 |
| Power IC(s) | TI TPS65994-AD |
| RAM Type | DDR4 |
| RAM Architecture | DDR4 SUB |
| RAM Quantity / Slots | 2 SODIMM |
| Card Reader IC | Realtek RTS5232S-GR |
| LAN IC | Intel GbE PHY JACKSONVILLE I219 |
| WiFi / WLAN IC | Intel AX201PD2WGQ |
| HDMI Level Shifter | Parade-PS8409A |
Technical Summary
This Lenovo T14/T15/P43s/P53s Gen2 LCFC NM-D351 Rev 1.0 schematic details an Intel Tiger Lake U platform with DDR4 SUB memory architecture supporting two SODIMM slots. The embedded controller is a MEC1503H-L1-I/3Y-TR BGA, with a dedicated W25Q80EWSNIGT EC flash ROM. The main BIOS SPI flash is a W25Q80DVUXIET with a total capacity of 32MB. Graphics are handled by an nVidia N18S-LP QN20-M dGPU. The charging IC is a BQ4179MWV-E2 in a WQFN56 package, and power delivery is managed by a TI TPS65994-AD controller. Audio is provided by an ALC3287-CG codec in a MQFN48 package. Connectivity includes an Intel GbE PHY Jacksonville I219 LAN IC, an Intel AX201PD2WGQ WiFi/WLAN module, and a Parade-PS8409A HDMI re-timer. The card reader is a Realtek RTS5232S-GR multimedia controller.
Technician FAQ
Q: What BIOS IC model is used on this motherboard?
A: The main BIOS SPI flash is a W25Q80DVUXIET with a total capacity of 32MB.
Q: What EC/KBC chip is used and is it programmable?
A: The embedded controller is a MEC1503H-L1-I/3Y-TR BGA. The schematic shows a dedicated W25Q80EWSNIGT SPI flash for the EC firmware, indicating the EC is programmable via its external flash.
Q: What is the charging IC and power architecture?
A: The charging IC is a BQ4179MWV-E2 in a WQFN56_7X7 package. Power delivery is managed by a TI TPS65994-AD PD controller.
Q: What is the memory configuration?
A: The board uses DDR4 SUB memory architecture with two SODIMM slots supporting up to DDR4 4266MHz.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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