sony z50cr mb s1202-2 mbx-266
Technical Specifications
Technical Summary
This Wistron Husk/Petra-4M schematic, dated September 6, 2012, documents an Ivy Bridge platform with a project code of 91.4TU01.001 and board number -4M. The system is built around an Intel CPU with 17W/GT2 graphics and supports both UMA and Muxless configurations, with a discrete Nvidia N13P-GL GPU featuring a 16-lane/128bit/29x29mm architecture. The embedded controller is an NPCE885, and the audio codec is an ALC271X. The BIOS is stored on an 8MB SPI Flash ROM. Power management is handled by a BQ24727 charger IC and a suite of DC/DC converters including ISL95836HRTZ, RT8223MGQW, TPS51218DSCR, RT8207LGQW, RT9025-25ZSP, ISL62882CHRTZ, and G978. Memory configuration consists of two DDRIII slots supporting 1600/1333 MHz on Channel A. The system integrates an RTL8411 for both LAN and card reader functions, and wireless connectivity is provided via 802.11a/b/g.
Technician FAQ
Q: What is the BIOS flash capacity on this motherboard?
A: The BIOS is stored on an 8MB SPI Flash ROM.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is an NPCE885.
Q: What is the discrete GPU on this motherboard?
A: The discrete GPU is an Nvidia N13P-GL with a 16-lane/128bit/29x29mm architecture.
Q: What is the charging IC on this motherboard?
A: The charging IC is a BQ24727.
Q: What memory type and configuration does this motherboard support?
A: The motherboard supports DDRIII memory with two slots on Channel A, running at 1600/1333 MHz.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Wistron Corporation |
| Model | Husk/Petra-4M |
| Motherboard Manufacturer | Wistron Corporation |
| Project Code | 91.4TU01.001 |
| Board Number | -4M |
| Revision | -4M |
| Date | Thursday, September 06, 2012 |
| CPU Platform | Ivy Bridge |
| PCH / Southbridge | |
| GPU Type | Nvidia N13P-GL |
| Graphics Architecture | 16 lane/128bit/29x29mm |
| EC / KBC | NPCE885 |
| Audio Codec | ALC271X |
| BIOS / SPI Flash | SPI Flash ROM 8MB |
| BIOS Flash Capacity | 8MB |
| Charging IC | BQ24727 |
| Charger Architecture | INPUTS DCBATOUT |
| Power IC(s) | ISL95836HRTZ, RT8223MGQW, TPS51218DSCR, RT8207LGQW, RT9025-25ZSP, ISL62882CHRTZ, G978 |
| RAM Type | DDRIII |
| RAM Architecture | 1600/1333 Channel A Slot 0, 1333/1600 Channel A Slot 1 |
| RAM Quantity / Slots | 2 |
| Card Reader IC | RTL8411 |
| LAN IC | RTL8411 |
| WiFi / WLAN IC | 802.11a/b/g |
Technical Summary
This Wistron Husk/Petra-4M schematic, dated September 6, 2012, documents an Ivy Bridge platform with a project code of 91.4TU01.001 and board number -4M. The system is built around an Intel CPU with 17W/GT2 graphics and supports both UMA and Muxless configurations, with a discrete Nvidia N13P-GL GPU featuring a 16-lane/128bit/29x29mm architecture. The embedded controller is an NPCE885, and the audio codec is an ALC271X. The BIOS is stored on an 8MB SPI Flash ROM. Power management is handled by a BQ24727 charger IC and a suite of DC/DC converters including ISL95836HRTZ, RT8223MGQW, TPS51218DSCR, RT8207LGQW, RT9025-25ZSP, ISL62882CHRTZ, and G978. Memory configuration consists of two DDRIII slots supporting 1600/1333 MHz on Channel A. The system integrates an RTL8411 for both LAN and card reader functions, and wireless connectivity is provided via 802.11a/b/g.
Technician FAQ
Q: What is the BIOS flash capacity on this motherboard?
A: The BIOS is stored on an 8MB SPI Flash ROM.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is an NPCE885.
Q: What is the discrete GPU on this motherboard?
A: The discrete GPU is an Nvidia N13P-GL with a 16-lane/128bit/29x29mm architecture.
Q: What is the charging IC on this motherboard?
A: The charging IC is a BQ24727.
Q: What memory type and configuration does this motherboard support?
A: The motherboard supports DDRIII memory with two slots on Channel A, running at 1600/1333 MHz.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Attachments
Last edited:
