acer aspire 5520 la-3581p icw50 mp r10 0415
Technical Specifications
Technical Summary
This Compal ICW50 / ICY70 LA-3581P Rev 1.0 motherboard schematic, dated 2007/04/15, documents an AMD Turion/Sempron CPU platform paired with an Nvidia MCP67-MV southbridge. The system memory architecture is DDRII Dual Channel with two SO-DIMM slots. The embedded controller is an ENE KB926. Audio is handled by an ALC268 HDA codec, and wired networking is provided by an RTL8211B Gigabit Ethernet PHY. A RICOH R5C833 card reader controller and an ADM1032AR thermal sensor are also present. The graphics subsystem is based on an MXM II VGA/BL module.
Technician FAQ
Q: What is the board number and project code for this motherboard?
A: The board number is LA-3581P, and the project code is ICW50.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is an ENE KB926.
Q: What is the memory architecture of this motherboard?
A: The memory architecture is DDRII Dual Channel with two SO-DIMM slots.
Q: What is the southbridge/PCH on this platform?
A: The southbridge is an Nvidia MCP67-MV.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Compal |
| Project Code | ICW50 |
| Board Number | LA-3581P |
| Revision | 1.0 |
| Date | 2007/04/15 |
| CPU Platform | AMD Turion/Sempron |
| PCH / Southbridge | Nvidia MCP67-MV |
| EC / KBC | ENE KB926 |
| Audio Codec | ALC268 |
| LAN IC | RTL8211B |
| Card Reader IC | RICOH R5C833 |
| Thermal Sensor | ADM1032AR |
| RAM Type | DDRII |
| RAM Architecture | Dual Channel |
| RAM Quantity / Slots | SO-DIMM X2 |
| Graphics Architecture | MXM II VGA/BL |
Technical Summary
This Compal ICW50 / ICY70 LA-3581P Rev 1.0 motherboard schematic, dated 2007/04/15, documents an AMD Turion/Sempron CPU platform paired with an Nvidia MCP67-MV southbridge. The system memory architecture is DDRII Dual Channel with two SO-DIMM slots. The embedded controller is an ENE KB926. Audio is handled by an ALC268 HDA codec, and wired networking is provided by an RTL8211B Gigabit Ethernet PHY. A RICOH R5C833 card reader controller and an ADM1032AR thermal sensor are also present. The graphics subsystem is based on an MXM II VGA/BL module.
Technician FAQ
Q: What is the board number and project code for this motherboard?
A: The board number is LA-3581P, and the project code is ICW50.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is an ENE KB926.
Q: What is the memory architecture of this motherboard?
A: The memory architecture is DDRII Dual Channel with two SO-DIMM slots.
Q: What is the southbridge/PCH on this platform?
A: The southbridge is an Nvidia MCP67-MV.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Attachments
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