acer aspire 5560 wistron je50-sb discrete_uma schematic
acer aspire 5560=1=wistron je50-sb discrete_uma.pdf
Technical Specifications
Technical Summary
This Wistron JE50_SB motherboard schematic, revision A3, dated April 1, 2011, is designed for the AMD LIANO CPU FS1 platform. The graphics architecture supports Discrete/UMA/Muxless configurations with AMD GPU Manhattan (Park/Madison M2) and Vancouver (Seymour/Whistler M2) options. The system utilizes an MXIC MX25L1605 SPI flash for BIOS storage and a KB3936 EC/KBC controller. Audio is handled by the ALC271X codec, while the BQ24745 manages battery charging. Power regulation is distributed across multiple ICs including the ISL6267, RT8208, RT8207, and RT8238. Memory architecture is DDR3 with a 4X4 configuration. Networking is provided by the BCM57785 Giga LAN controller, and the board includes a 5-in-1 card reader supporting MS/MS Pro/xD/MMC/SD formats.
Technician FAQ
Q: What BIOS IC model is used on this motherboard?
A: The BIOS SPI flash is an MXIC MX25L1605.
Q: What EC/KBC controller is used on this motherboard?
A: The EC/KBC controller is a KB3936.
Q: What is the charging IC on this motherboard?
A: The charging IC is a BQ24745.
Q: What is the audio codec on this motherboard?
A: The audio codec is an ALC271X.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
acer aspire 5560=1=wistron je50-sb discrete_uma.pdf
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Wistron Corporation |
| Project Code | JE50_SB |
| Document Number | A4 |
| Revision | A3 |
| Date | Friday, April 01, 2011 |
| CPU Platform | AMD LIANO CPU FS1 |
| GPU Type | AMD GPU Manhattan(Park/Madison M2) and Vancouver(Seymour/Whistler M2) |
| Graphics Architecture | Discrete/UMA /Muxless |
| EC / KBC | KB3936 |
| Audio Codec | ALC271X |
| BIOS / SPI Flash | MXIC MX25L1605 |
| Charging IC | BQ24745 |
| Power IC(s) | ISL6267, RT8208, RT8207, RT8238, RT9025, RT9024, RT9025 |
| RAM Type | DDR3 |
| RAM Architecture | 4X4 |
| LAN IC | BCM57785 |
| WiFi / WLAN IC | WLAN |
| Card Reader IC | 5 in 1 MS/MS Pro/xD/MMC/SD |
| USB Hub IC | USB 3.0 3 PORT |
Technical Summary
This Wistron JE50_SB motherboard schematic, revision A3, dated April 1, 2011, is designed for the AMD LIANO CPU FS1 platform. The graphics architecture supports Discrete/UMA/Muxless configurations with AMD GPU Manhattan (Park/Madison M2) and Vancouver (Seymour/Whistler M2) options. The system utilizes an MXIC MX25L1605 SPI flash for BIOS storage and a KB3936 EC/KBC controller. Audio is handled by the ALC271X codec, while the BQ24745 manages battery charging. Power regulation is distributed across multiple ICs including the ISL6267, RT8208, RT8207, and RT8238. Memory architecture is DDR3 with a 4X4 configuration. Networking is provided by the BCM57785 Giga LAN controller, and the board includes a 5-in-1 card reader supporting MS/MS Pro/xD/MMC/SD formats.
Technician FAQ
Q: What BIOS IC model is used on this motherboard?
A: The BIOS SPI flash is an MXIC MX25L1605.
Q: What EC/KBC controller is used on this motherboard?
A: The EC/KBC controller is a KB3936.
Q: What is the charging IC on this motherboard?
A: The charging IC is a BQ24745.
Q: What is the audio codec on this motherboard?
A: The audio codec is an ALC271X.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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