Schematic acer pegatron ma50 rev1.0 schematic

Admin

Founder
Staff member
Admin

Reputation:

acer pegatron ma50_rev1.0 schematic

acer=1=pegatron ma50_rev1.0.pdf




Technical Specifications

ParameterValue
BrandJoyoung_Chianhg
ModelMA50
Project NameMA50
Revision1.0
DateMonday, February 13, 2012
CPU PlatformSandy Bridge
PCH / SouthbridgePanther Point
GPU TypenVidia N13PGL
EC / KBCNPCE795L
Audio CodecALC271
RAM TypeDDR3
RAM ArchitectureDDR3 SO-DIMM
RAM Quantity / Slots2
Card Reader ICRealtek RTS5209
LAN ICBroadcom BCM57780
WiFi / WLAN ICWLAN + BT
Charger ArchitectureCharger(4M+2M)

Technical Summary

The Joyoung_Chianhg MA50 Ultrabook schematic, revision 1.0 dated February 13, 2012, is built on the Intel Sandy Bridge CPU platform paired with the Panther Point PCH. Graphics are handled by a discrete nVidia N13PGL GPU with dedicated VRAM. System management is controlled by an NPCE795L EC/KBC. Audio is provided by an ALC271 Azalia codec. Memory configuration consists of two DDR3 SO-DIMM slots. Networking includes a Broadcom BCM57780 GigaLAN controller and a WLAN + Bluetooth MiniCard module. A Realtek RTS5209 controller manages the 2-in-1 card reader. The charging architecture is specified as Charger(4M+2M).

Technician FAQ

Q: What EC/KBC is used on this MA50 motherboard?

A: The schematic specifies an NPCE795L EC/KBC.

Q: What audio codec is used on this motherboard?

A: The audio codec is an ALC271 Azalia Codec.

Q: What discrete GPU is used on this MA50 Ultrabook?

A: The schematic specifies an nVidia N13PGL GPU.

Q: What LAN controller is used on this motherboard?

A: The LAN controller is a Broadcom BCM57780 GigaLAN.

Q: What card reader controller is used?

A: The card reader controller is a Realtek RTS5209.

Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
 

Attachments

  • Acer=1=Pegatron MA50_Rev1.0.zip
    2.1 MB · Views: 13
Last edited:
Who is viewing this thread?

There are currently 0 members watching this topic

Users who has read this topic
Top