dell-3446 cedar_intel_mb_reva00 schematic
dell-3446=1=cedar_intel_mb_reva00.pdf
Technical Specifications
Technical Summary
This Wistron Janus HSW 40/50/70 motherboard, project code 4PD00I010001 and PCB number 13302-1 revision A00, is designed for Broadwell ULT processors. The platform supports a discrete NVIDIA N15V-GM-S-A2 GPU with DIS-only graphics architecture. System memory consists of four DDR3L SODIMM modules. The embedded controller is a Nuvoton NPCE285P, and the audio codec is an ALC3234. The BIOS is stored on an 8MB Quad Read SPI flash. Power management is handled by a TPS51225RUKR-GP charger with DCBATOUT architecture, alongside multiple power ICs including the ISL95813HRZ-GP, HPA02224RGRR-1-GP, RT8237CZQW-2-GP, and TLV70215DBVR-GP. Networking is provided by either a Realtek RTL8106E (Cedar) or RTL8111G (Janus) LAN controller, with an 802.11a/b/g/n BT V4.0 combo wireless module. The card reader uses a Realtek RTS5170, and the HDMI level shifter is an RTD2168.
Technician FAQ
Q: What is the board number and project code for this motherboard?
A: The board number is 13302-1, and the project code is Janus HSW 40/50/70 with document number 4PD00I010001.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is a Nuvoton NPCE285P.
Q: What is the charging architecture and charger IC?
A: The charger architecture is DCBATOUT, using a TPS51225RUKR-GP IC.
Q: What is the graphics configuration on this board?
A: This board uses a discrete NVIDIA N15V-GM-S-A2 GPU (DIS only) with no UMA support.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
dell-3446=1=cedar_intel_mb_reva00.pdf
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Wistron Corporation |
| Project Code | Janus HSW 40/50/70 |
| Board Number | 13302-1 |
| Revision | A00 |
| Date | Friday, February 07, 2014 |
| Document Number | 4PD00I010001 |
| CPU Platform | Broadwell ULT |
| CPU Model | CPU1B HASWELL-6-GP-U71.HASWE.G0U |
| GPU Type | NVIDIA N15V-GM-S-A2 GB2-64 (23x23) 25W |
| Graphics Architecture | DIS only |
| EC / KBC | NPCE285P |
| EC/KBC Package | NUVOTON |
| Audio Codec | ALC3234 |
| BIOS / SPI Flash | 8MB Quad Read |
| Charging IC | TPS51225RUKR-GP |
| Charger Architecture | DCBATOUT |
| Power IC(s) | ISL95813HRZ-GP, HPA02224RGRR-1-GP, RT8237CZQW-2-GP, TLV70215DBVR-GP |
| RAM Type | DDR3L |
| RAM Architecture | SODIMM |
| RAM Quantity / Slots | 2GB *4 |
| Card Reader IC | RTS5170 |
| LAN IC | RTL8106E (Cedar), RTL8111G (Janus) |
| WiFi / WLAN IC | 802.11a/b/g/n BT V4.0 combo |
| HDMI Level Shifter | RTD2168 |
Technical Summary
This Wistron Janus HSW 40/50/70 motherboard, project code 4PD00I010001 and PCB number 13302-1 revision A00, is designed for Broadwell ULT processors. The platform supports a discrete NVIDIA N15V-GM-S-A2 GPU with DIS-only graphics architecture. System memory consists of four DDR3L SODIMM modules. The embedded controller is a Nuvoton NPCE285P, and the audio codec is an ALC3234. The BIOS is stored on an 8MB Quad Read SPI flash. Power management is handled by a TPS51225RUKR-GP charger with DCBATOUT architecture, alongside multiple power ICs including the ISL95813HRZ-GP, HPA02224RGRR-1-GP, RT8237CZQW-2-GP, and TLV70215DBVR-GP. Networking is provided by either a Realtek RTL8106E (Cedar) or RTL8111G (Janus) LAN controller, with an 802.11a/b/g/n BT V4.0 combo wireless module. The card reader uses a Realtek RTS5170, and the HDMI level shifter is an RTD2168.
Technician FAQ
Q: What is the board number and project code for this motherboard?
A: The board number is 13302-1, and the project code is Janus HSW 40/50/70 with document number 4PD00I010001.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is a Nuvoton NPCE285P.
Q: What is the charging architecture and charger IC?
A: The charger architecture is DCBATOUT, using a TPS51225RUKR-GP IC.
Q: What is the graphics configuration on this board?
A: This board uses a discrete NVIDIA N15V-GM-S-A2 GPU (DIS only) with no UMA support.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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