dell inspiron n4020 dj1-monteviana-uma-09275-1 intel gm45 1
Technical Specifications
Technical Summary
This Wistron DJ1 INTEL IO Board, revision A00, is based on the Intel GM45+ICH9M platform supporting a uFCPGA Mobile Penryn processor. The board is identified by project code 91.4EK01.001 and PCB number 09783-1, with PCB part number 48.4EK13.0SB. The schematic document number is A31, dated February 23, 2010. The board includes a DC-in connector (DCIN1, SKT-JACK-204-GP-U, 22.10037.D61) and a main IO board connector (IOBD2, ACES-CONN60E-1-GP). Power input is managed through a P-channel MOSFET (PU201, AO4407-GP) and a TVS diode (PD201, 1SMB22AT3G-GP-U). The design includes multiple depopulation options for components such as EC203, EC209, EC213, and others, as well as "Do Not Stuff" positions for several resistors and capacitors.
Technician FAQ
Q: What is the platform architecture of this Wistron DJ1 IO Board?
A: The board uses the Intel GM45+ICH9M chipset platform, supporting a uFCPGA Mobile Penryn processor.
Q: What are the key board identification numbers for this schematic?
A: The project code is 91.4EK01.001, the PCB number is 09783-1, the PCB part number is 48.4EK13.0SB, and the document number is A31.
Q: What is the revision and date of this schematic?
A: The schematic is revision A00, dated Tuesday, February 23, 2010.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
Technical Summary
The Wistron DJ1 Montevina UMA motherboard, project code 91.4EK01.001 and board number 48.4EK06.0SA revision 09275-SA, is built around the Intel GM45+ICH9M platform supporting a Socket P Intel Mobile Penryn CPU. Graphics are integrated via the GM45 UMA architecture. The system utilizes dual-channel DDRIII 800/1066 memory across two slots. The embedded controller is a Nuvoton NPCE781BA0DX, and the audio codec is an IDT92HD79B1. Power management is handled by a BQ24745 charger and multiple DC/DC converters including TPS51620, TPS51116, TPS51125, and TPS51218. The BIOS is stored on a 2MB Flash ROM. Networking is provided by an AR8132 LAN IC and an 802.11a/b/g Mini-Card WLAN. A Realtek RTS5138 card reader and an EMC2102 thermal sensor are also present.
Technician FAQ
Q: What is the board number and project code for this motherboard?
A: The board number is 48.4EK06.0SA, and the project code is 91.4EK01.001.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is a Nuvoton NPCE781BA0DX.
Q: What is the BIOS flash configuration?
A: The BIOS is stored on a 2MB Flash ROM.
Q: What charging IC and architecture are used?
A: The charging IC is a BQ24745, part of the MAXIM CHARGER architecture.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
Technical Summary
The Wistron DJ1 Montevina UMA motherboard, project code 91.4EK01.001 with board number 48.4EK06.0SA revision 09275-SA/A00, is built on the Intel GM45+ICH9M platform supporting an Intel Mobile CPU in Socket P. Graphics are integrated via the GM45 UMA architecture. The system uses dual-channel DDRIII 800/1066 memory across two slots. The embedded controller is an NPCE781BA0DX from NUVOTON. Audio is handled by an IDT92HD79B1 codec. The BIOS is stored on a 2MB Flash ROM. Power management includes a BQ24745 charger and multiple TPS-series DC/DC converters. Networking is provided by an AR8132 10/100 NIC and an 802.11a/b/g Mini-Card. A Realtek RTS5138 card reader supports SD/MMC/MS/MS Pro/xD formats.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is an NPCE781BA0DX from NUVOTON.
Q: What is the BIOS flash configuration?
A: The BIOS is stored on a 2MB Flash ROM connected via the LPC bus.
Q: What is the memory architecture?
A: The motherboard supports dual-channel DDRIII 800/1066 memory across two SO-DIMM slots.
Q: What charging IC is used?
A: The charger IC is a BQ24745 from Texas Instruments.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
Technical Summary
The Wistron DJ1 Montevina UMA (Project Code 91.4EK01.001, Board Number 48.4EK06.0SA, Revision A00) is a laptop motherboard designed around the Intel GM45+ICH9M chipset platform, supporting Socket P Intel Mobile CPUs. Graphics are integrated via the GM45 architecture. The system utilizes two DDRIII 800/1066 memory slots in a dual-channel configuration. Power management is handled by a BQ24745 charger IC and multiple DC/DC converters including TPS51125, TPS51218, TPS51116, and TPS51620. The embedded controller is a Nuvoton NPCE781BA0DX. Audio is provided by an IDT92HD79B1 codec. The BIOS is stored on a 2MB Flash ROM. Networking includes an Atheros AR8132 10/100 NIC and an 802.11a/b/g Mini-Card WLAN. A Realtek RTS5138 card reader supports SD/MMC/MS/MS Pro/xD formats.
Technician FAQ
Q: What is the board number and project code for this motherboard?
A: The board number is 48.4EK06.0SA, and the project code is 91.4EK01.001.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is a Nuvoton NPCE781BA0DX.
Q: What is the BIOS flash configuration?
A: The BIOS is stored on a 2MB Flash ROM.
Q: What charging IC and power management ICs are used?
A: The charging IC is a BQ24745. Power management ICs include TPS51125, TPS51218, TPS51116, and TPS51620.
Q: What memory type and configuration does this board support?
A: The board supports DDRIII 800/1066 memory in a dual-channel configuration across two slots.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
Technical Summary
This Wistron Corporation motherboard schematic, dated December 10, 2009, is built around the ICH9M platform. The document details the DJ MV UMA power-up sequence, specifying critical timing and voltage ramp requirements for the ICH9M southbridge. Key power rails include +3.3V_ALW, +5V_ALW, +3.3V_RUN, +5V_RUN, +1.5V_RUN, +1.05V_VCCP, and VCC_CORE. The schematic enforces strict sequencing rules, such as +5V_ALW ramping before +3.3V_ALW, and +5V_RUN ramping before +3.3V_RUN, with a maximum voltage difference of 0.7V. Timing constraints require VRMPWRGD to precede PM_PWROK by at least 3ms, and PM_PWROK to precede PLTRST# by 1ms to 2.2ms. The power sequence is initiated by KBC_PWRBTN# and PM_PWRBTN# signals, with AC adapter insertion and pre-boot CPU VID value configuration.
Technician FAQ
Q: What is the platform architecture of this motherboard?
A: The motherboard is based on the ICH9M platform.
Q: What are the critical power sequencing rules for this motherboard?
A: The schematic specifies that +5V_ALW must ramp before +3.3V_ALW, and +5V_RUN must ramp before +3.3V_RUN, with a maximum voltage difference of 0.7V. Additionally, +1.5V_RUN must ramp before +1.05V_VCCP.
Q: What are the timing constraints for PM_PWROK and PLTRST#?
A: VRMPWRGD must come up at least 3ms before PM_PWROK, and PM_PWROK must come up between 1ms and 2.2ms before PLTRST#.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Wistron Corporation |
| Model | DJ1 INTEL IO Board |
| Motherboard Manufacturer | Wistron Corporation |
| Project Code | 91.4EK01.001 |
| Board Number | DJ1 IO Board |
| Revision | A00 |
| Date | Tuesday, February 23, 2010 |
| CPU Platform | Intel GM45+[URL="https://dr-bios.com/components/cpu-platform/ich9m/"]ICH9M[/URL] |
| Document Number | A31 |
| PCB Number | 09783-1 |
| PCB P/N | 48.4EK13.0SB |
Technical Summary
This Wistron DJ1 INTEL IO Board, revision A00, is based on the Intel GM45+ICH9M platform supporting a uFCPGA Mobile Penryn processor. The board is identified by project code 91.4EK01.001 and PCB number 09783-1, with PCB part number 48.4EK13.0SB. The schematic document number is A31, dated February 23, 2010. The board includes a DC-in connector (DCIN1, SKT-JACK-204-GP-U, 22.10037.D61) and a main IO board connector (IOBD2, ACES-CONN60E-1-GP). Power input is managed through a P-channel MOSFET (PU201, AO4407-GP) and a TVS diode (PD201, 1SMB22AT3G-GP-U). The design includes multiple depopulation options for components such as EC203, EC209, EC213, and others, as well as "Do Not Stuff" positions for several resistors and capacitors.
Technician FAQ
Q: What is the platform architecture of this Wistron DJ1 IO Board?
A: The board uses the Intel GM45+ICH9M chipset platform, supporting a uFCPGA Mobile Penryn processor.
Q: What are the key board identification numbers for this schematic?
A: The project code is 91.4EK01.001, the PCB number is 09783-1, the PCB part number is 48.4EK13.0SB, and the document number is A31.
Q: What is the revision and date of this schematic?
A: The schematic is revision A00, dated Tuesday, February 23, 2010.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Wistron Corporation |
| Model | DJ1 Montevina UMA |
| Motherboard Manufacturer | Wistron Corporation |
| Project Code | 91.4EK01.001 |
| Board Number | 48.4EK06.0SA |
| Revision | 09275-SA |
| Date | 2010-02-10 |
| CPU Platform | Intel GM45+[URL="https://dr-bios.com/components/cpu-platform/ich9m/"]ICH9M[/URL] |
| CPU Socket | Socket P |
| CPU Model | [URL="https://dr-bios.com/components/cpu-model/intel-mobile-cpu/"]Intel Mobile CPU Penryn[/URL] |
| PCH / Southbridge | ICH9-M |
| GPU Type | Integrated (UMA) |
| Graphics Architecture | GM45 |
| EC / KBC | NPCE781BA0DX |
| EC/KBC Package | NUVOTON |
| Audio Codec | IDT92HD79B1 |
| BIOS / SPI Flash | 2MB Flash ROM |
| Charging IC | BQ24745 |
| Charger Architecture | MAXIM CHARGER |
| Power IC(s) | TPS51620, TPS51116, TPS51125, TPS51218, TPS51620 |
| RAM Type | DDRIII 800/1066 |
| RAM Architecture | Dual Channel |
| RAM Quantity / Slots | 2 |
| Card Reader IC | Realtek RTS5138 |
| LAN IC | AR8132 |
| WiFi / WLAN IC | 802.11a/b/g Mini-Card |
| Thermal Sensor | EMC2102 |
Technical Summary
The Wistron DJ1 Montevina UMA motherboard, project code 91.4EK01.001 and board number 48.4EK06.0SA revision 09275-SA, is built around the Intel GM45+ICH9M platform supporting a Socket P Intel Mobile Penryn CPU. Graphics are integrated via the GM45 UMA architecture. The system utilizes dual-channel DDRIII 800/1066 memory across two slots. The embedded controller is a Nuvoton NPCE781BA0DX, and the audio codec is an IDT92HD79B1. Power management is handled by a BQ24745 charger and multiple DC/DC converters including TPS51620, TPS51116, TPS51125, and TPS51218. The BIOS is stored on a 2MB Flash ROM. Networking is provided by an AR8132 LAN IC and an 802.11a/b/g Mini-Card WLAN. A Realtek RTS5138 card reader and an EMC2102 thermal sensor are also present.
Technician FAQ
Q: What is the board number and project code for this motherboard?
A: The board number is 48.4EK06.0SA, and the project code is 91.4EK01.001.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is a Nuvoton NPCE781BA0DX.
Q: What is the BIOS flash configuration?
A: The BIOS is stored on a 2MB Flash ROM.
Q: What charging IC and architecture are used?
A: The charging IC is a BQ24745, part of the MAXIM CHARGER architecture.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Wistron Corporation |
| Model | DJ1 Montevina UMA |
| Motherboard Manufacturer | Wistron Corporation |
| Project Code | 91.4EK01.001 |
| Board Number | 48.4EK06.0SA |
| Revision | 09275-SA / A00 |
| Date | Wednesday, February 24, 2010 |
| CPU Platform | Intel GM45+[URL="https://dr-bios.com/components/cpu-platform/ich9m/"]ICH9M[/URL] |
| CPU Model | [URL="https://dr-bios.com/components/cpu-model/intel-mobile-cpu/"]Intel Mobile CPU Socket P[/URL] |
| CPU Socket | Socket P |
| PCH / Southbridge | ICH9-M |
| GPU Type | Integrated (UMA) |
| Graphics Architecture | GM45 |
| EC / KBC | NPCE781BA0DX |
| Audio Codec | IDT92HD79B1 |
| BIOS / SPI Flash | 2MB Flash ROM |
| Charging IC | BQ24745 |
| Charger Architecture | MAXIM CHARGER |
| Power IC(s) | TPS51620, TPS51116, TPS51125, TPS51218, TPS51620 |
| RAM Type | DDRIII 800/1066 |
| RAM Architecture | Dual Channel |
| RAM Quantity / Slots | 2 |
| Card Reader IC | Realtek RTS5138 |
| LAN IC | AR8132 |
| WiFi / WLAN IC | 802.11a/b/g Mini-Card |
Technical Summary
The Wistron DJ1 Montevina UMA motherboard, project code 91.4EK01.001 with board number 48.4EK06.0SA revision 09275-SA/A00, is built on the Intel GM45+ICH9M platform supporting an Intel Mobile CPU in Socket P. Graphics are integrated via the GM45 UMA architecture. The system uses dual-channel DDRIII 800/1066 memory across two slots. The embedded controller is an NPCE781BA0DX from NUVOTON. Audio is handled by an IDT92HD79B1 codec. The BIOS is stored on a 2MB Flash ROM. Power management includes a BQ24745 charger and multiple TPS-series DC/DC converters. Networking is provided by an AR8132 10/100 NIC and an 802.11a/b/g Mini-Card. A Realtek RTS5138 card reader supports SD/MMC/MS/MS Pro/xD formats.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is an NPCE781BA0DX from NUVOTON.
Q: What is the BIOS flash configuration?
A: The BIOS is stored on a 2MB Flash ROM connected via the LPC bus.
Q: What is the memory architecture?
A: The motherboard supports dual-channel DDRIII 800/1066 memory across two SO-DIMM slots.
Q: What charging IC is used?
A: The charger IC is a BQ24745 from Texas Instruments.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Wistron Corporation |
| Model | DJ1 Montevina UMA |
| Motherboard Manufacturer | Wistron Corporation |
| Project Code | 91.4EK01.001 |
| Board Number | 48.4EK06.0SA |
| Revision | A00 |
| Date | Wednesday, February 24, 2010 |
| CPU Platform | Intel GM45+[URL="https://dr-bios.com/components/cpu-platform/ich9m/"]ICH9M[/URL] |
| CPU Model | Intel Mobile CPU |
| CPU Socket | Socket P |
| PCH / Southbridge | ICH9-M |
| GPU Type | Integrated |
| Graphics Architecture | GM45 |
| EC / KBC | NPCE781BA0DX |
| EC/KBC Package | NUVOTON |
| Audio Codec | IDT92HD79B1 |
| BIOS / SPI Flash | 2MB Flash ROM |
| Charging IC | BQ24745 |
| Charger Architecture | MAXIM CHARGER |
| Power IC(s) | TPS51125, TPS51218, TPS51116, TPS51620 |
| RAM Type | DDRIII 800/1066 |
| RAM Architecture | Dual Channel |
| RAM Quantity / Slots | 2 |
| Card Reader IC | Realtek RTS5138 |
| LAN IC | AR8132 |
| WiFi / WLAN IC | 802.11a/b/g Mini-Card |
Technical Summary
The Wistron DJ1 Montevina UMA (Project Code 91.4EK01.001, Board Number 48.4EK06.0SA, Revision A00) is a laptop motherboard designed around the Intel GM45+ICH9M chipset platform, supporting Socket P Intel Mobile CPUs. Graphics are integrated via the GM45 architecture. The system utilizes two DDRIII 800/1066 memory slots in a dual-channel configuration. Power management is handled by a BQ24745 charger IC and multiple DC/DC converters including TPS51125, TPS51218, TPS51116, and TPS51620. The embedded controller is a Nuvoton NPCE781BA0DX. Audio is provided by an IDT92HD79B1 codec. The BIOS is stored on a 2MB Flash ROM. Networking includes an Atheros AR8132 10/100 NIC and an 802.11a/b/g Mini-Card WLAN. A Realtek RTS5138 card reader supports SD/MMC/MS/MS Pro/xD formats.
Technician FAQ
Q: What is the board number and project code for this motherboard?
A: The board number is 48.4EK06.0SA, and the project code is 91.4EK01.001.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is a Nuvoton NPCE781BA0DX.
Q: What is the BIOS flash configuration?
A: The BIOS is stored on a 2MB Flash ROM.
Q: What charging IC and power management ICs are used?
A: The charging IC is a BQ24745. Power management ICs include TPS51125, TPS51218, TPS51116, and TPS51620.
Q: What memory type and configuration does this board support?
A: The board supports DDRIII 800/1066 memory in a dual-channel configuration across two slots.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Wistron Corporation |
| Motherboard Manufacturer | Wistron Corporation |
| Date | Thursday, December 10, 2009 |
| CPU Platform | ICH9M |
| PCH / Southbridge | ICH9M |
Technical Summary
This Wistron Corporation motherboard schematic, dated December 10, 2009, is built around the ICH9M platform. The document details the DJ MV UMA power-up sequence, specifying critical timing and voltage ramp requirements for the ICH9M southbridge. Key power rails include +3.3V_ALW, +5V_ALW, +3.3V_RUN, +5V_RUN, +1.5V_RUN, +1.05V_VCCP, and VCC_CORE. The schematic enforces strict sequencing rules, such as +5V_ALW ramping before +3.3V_ALW, and +5V_RUN ramping before +3.3V_RUN, with a maximum voltage difference of 0.7V. Timing constraints require VRMPWRGD to precede PM_PWROK by at least 3ms, and PM_PWROK to precede PLTRST# by 1ms to 2.2ms. The power sequence is initiated by KBC_PWRBTN# and PM_PWRBTN# signals, with AC adapter insertion and pre-boot CPU VID value configuration.
Technician FAQ
Q: What is the platform architecture of this motherboard?
A: The motherboard is based on the ICH9M platform.
Q: What are the critical power sequencing rules for this motherboard?
A: The schematic specifies that +5V_ALW must ramp before +3.3V_ALW, and +5V_RUN must ramp before +3.3V_RUN, with a maximum voltage difference of 0.7V. Additionally, +1.5V_RUN must ramp before +1.05V_VCCP.
Q: What are the timing constraints for PM_PWROK and PLTRST#?
A: VRMPWRGD must come up at least 3ms before PM_PWROK, and PM_PWROK must come up between 1ms and 2.2ms before PLTRST#.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Indexed motherboard components
Open a component to see every indexed schematic that uses the same part.
91.4EK01.001
Project Code
DJ1 IO BOARD
Board Number
GM45ICH9M
CPU Platform
09783-1
Board Number
48.4EK06.0SA
Board Number
Intel Mobile CPU Penryn
CPU Model
ICH9
PCH / Southbridge
GM45
Graphics
NPCE781BA0DX
EC / KBC
IDT92HD79B1
Audio Codec
BQ24745
Charging / PD IC
TPS51116
Power IC
TPS51125
Power IC
TPS51218
Power IC
TPS51620
Power IC
DDR3
RAM Type
RTS5138
Card Reader IC
AR8132
LAN Controller
EMC2102
Thermal / Fan Control
Intel Mobile CPU Socket P
CPU Model
Intel Mobile CPU
CPU Model
ICH9M
CPU Platform
ICH9M
PCH / Southbridge
Indexed motherboard components
Open a component to see every indexed schematic that uses the same part.
91.4EK01.001
Project Code
DJ1 IO BOARD
Board Number
GM45ICH9M
CPU Platform
09783-1
Board Number
48.4EK06.0SA
Board Number
Intel Mobile CPU Penryn
CPU Model
ICH9
PCH / Southbridge
GM45
Graphics
NPCE781BA0DX
EC / KBC
IDT92HD79B1
Audio Codec
BQ24745
Charging / PD IC
TPS51116
Power IC
TPS51125
Power IC
TPS51218
Power IC
TPS51620
Power IC
DDR3
RAM Type
RTS5138
Card Reader IC
AR8132
LAN Controller
EMC2102
Thermal / Fan Control
Intel Mobile CPU Socket P
CPU Model
Intel Mobile CPU
CPU Model
ICH9M
CPU Platform
ICH9M
PCH / Southbridge
Attachments
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