dell inspiron n5040 wistron enrico caruso 15 cp_reva00 schematic
dell inspiron n5040=1=wistron enrico caruso 15 cp_reva00.pdf
Technical Specifications
Technical Summary
This Wistron Corporation Enrico/Caruso 15" UMA schematic, document number A00, dated April 22, 2011, details a motherboard built on the Intel Ibex Peak-M platform with an rPGA988A socket for Arrandale processors. The board number is 48.4IP01.011 with project code 91.4IP01.001 and revision 10263-1. Graphics are UMA, integrated into the Arrandale CPU. The system uses two DDRIII 1066 memory slots configured as Channel A and Channel B. The embedded controller is a Nuvoton NPCE781BA0DXN in a VOTON package. The BIOS is stored on a 4MB SPI flash ROM. Power management is handled by a BQ24707 charger IC, with system DC/DC converters including ISL62882, RT8207, RT8237A, TPS51123, TPS51611, and APW7153B. Audio is provided by an IDT92HD87B1P codec. Networking includes a Realtek RTL8105E-VC 10/100 NIC and a Mini-Card for 802.11b/g/n with Bluetooth V3.0+HS. A Realtek RTS5138 card reader supports SD/MMC/MS.
Technician FAQ
Q: What is the BIOS flash configuration on this motherboard?
A: The BIOS is stored on a 4MB SPI flash ROM, connected via the SPI bus to the PCH.
Q: What EC/KBC is used and is it programmable?
A: The EC/KBC is a Nuvoton NPCE781BA0DXN in a VOTON package. The schematic does not explicitly indicate ISP or dedicated programming circuitry for the EC.
Q: What is the memory architecture?
A: The motherboard supports two DDRIII 1066 SO-DIMM slots, configured as Channel A (Slot 0) and Channel B (Slot 1).
dell inspiron n5040=1=wistron enrico caruso 15 cp_reva00.pdf
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Wistron Corporation |
| Model | Enrico/Caruso 15" UMA |
| Motherboard Manufacturer | Wistron Corporation |
| Project Code | 91.4IP01.001 |
| Board Number | 48.4IP01.011 |
| Revision | 10263-1 |
| Date | Friday, April 22, 2011 |
| CPU Platform | Intel Ibex Peak-M / Arrandale |
| CPU Socket | rPGA988A |
| PCH / Southbridge | Intel Ibex Peak-M |
| GPU Type | UMA |
| Graphics Architecture | Arrandale |
| EC / KBC | NPCE781BA0DXN |
| EC/KBC Package | VOTON |
| Audio Codec | IDT92HD87B1P |
| BIOS / SPI Flash | 4MB Flash ROM |
| Charging IC | BQ24707 |
| Charger Architecture | MAXIM CHARGER |
| Power IC(s) | ISL62882, RT8207, RT8237A, TPS51123, TPS51611, APW7153B |
| RAM Type | DDRIII |
| RAM Architecture | DDRIII 1066 Channel A, DDRIII 1066 Channel B |
| RAM Quantity / Slots | Slot 0, Slot 1 |
| Card Reader IC | Realtek RTS5138 |
| LAN IC | Realtek RTL8105E-VC |
| WiFi / WLAN IC | 802.11b/g/n BT V3.0+HS Mini-Card |
| Document Number | A00 |
Technical Summary
This Wistron Corporation Enrico/Caruso 15" UMA schematic, document number A00, dated April 22, 2011, details a motherboard built on the Intel Ibex Peak-M platform with an rPGA988A socket for Arrandale processors. The board number is 48.4IP01.011 with project code 91.4IP01.001 and revision 10263-1. Graphics are UMA, integrated into the Arrandale CPU. The system uses two DDRIII 1066 memory slots configured as Channel A and Channel B. The embedded controller is a Nuvoton NPCE781BA0DXN in a VOTON package. The BIOS is stored on a 4MB SPI flash ROM. Power management is handled by a BQ24707 charger IC, with system DC/DC converters including ISL62882, RT8207, RT8237A, TPS51123, TPS51611, and APW7153B. Audio is provided by an IDT92HD87B1P codec. Networking includes a Realtek RTL8105E-VC 10/100 NIC and a Mini-Card for 802.11b/g/n with Bluetooth V3.0+HS. A Realtek RTS5138 card reader supports SD/MMC/MS.
Technician FAQ
Q: What is the BIOS flash configuration on this motherboard?
A: The BIOS is stored on a 4MB SPI flash ROM, connected via the SPI bus to the PCH.
Q: What EC/KBC is used and is it programmable?
A: The EC/KBC is a Nuvoton NPCE781BA0DXN in a VOTON package. The schematic does not explicitly indicate ISP or dedicated programming circuitry for the EC.
Q: What is the memory architecture?
A: The motherboard supports two DDRIII 1066 SO-DIMM slots, configured as Channel A (Slot 0) and Channel B (Slot 1).
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