Salim Badakhshan
Registered
Reputation:
Dell Wistron SouthPeak15 TGL SB 19819 Schematic
Technical Specifications
Technical Summary
The Wistron South Peak 15" motherboard, project code 4PD0M6010001 and board number 19819 revision SB, is built around the Intel Tiger Lake-UP3 CPU platform paired with a TGL U PCH-LP southbridge. Graphics are handled by a discrete NVIDIA N18S-G5 GPU with GDDR6 VRAM. The system firmware is stored on a Winbond W25R256JVEIQ 32MB SPI flash in a WSON package, while the SMSC MEC 5200 EC uses a separate Winbond WQ64JVZPIQ 8MB flash ROM. Memory configuration consists of two DDR4x SODIMM slots. The board integrates a Realtek ALC3204 audio codec, a Realtek RTS5242 card reader, an Intel WGI219LM LAN controller, and a Broadcom BCM58202CV3 wireless module. USB-C power delivery and charging are managed by a TI TPS65994 controller, and Thunderbolt 3/USB3.1/DP 1.4 connectivity is provided by an Intel JHL8040R retimer. HDMI output is handled by a PS8409A retimer.
Technician FAQ
Q: What BIOS IC model is used on this motherboard?
A: The BIOS flash is a Winbond W25R256JVEIQ (32MB) in a WSON package.
Q: What EC/KBC chip is used and is it programmable?
A: The EC/KBC is a SMSC MEC 5200. The schematic shows a dedicated Winbond WQ64JVZPIQ (8MB) flash ROM for the EC, indicating it is programmable via SPI.
Q: What is the discrete GPU configuration?
A: The motherboard uses an NVIDIA N18S-G5 GPU with 2GB of GDDR6 VRAM.
Q: What is the charging architecture?
A: USB-C power delivery and charging are controlled by a TI TPS65994 controller.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Wistron Corporation |
| Model | South Peak 15" |
| Motherboard Manufacturer | Wistron Corporation |
| Project Code | 4PD0M6010001 |
| Board Number | 19819 |
| Revision | SB |
| Date | 2020-04-24 |
| CPU Platform | Tiger Lake-UP3 |
| PCH / Southbridge | TGL U PCH-LP |
| GPU Type | NVIDIA N18S-G5 |
| Graphics Architecture | GDDR6 |
| EC / KBC | SMSC MEC 5200 |
| Audio Codec | RealTek ALC3204 |
| BIOS Flash Exact Model | W25R256JVEIQ (32MB) |
| BIOS Flash Package | WSON |
| EC Flash / ROM | Winbond WQ64JVZPIQ (8MB) |
| Charging IC | TI TPS65994 |
| RAM Type | DDR4x |
| RAM Architecture | SODIMM |
| RAM Quantity / Slots | 2 |
| Card Reader IC | Realtek RTS5242 |
| LAN IC | Intel WGI219LM |
| WiFi / WLAN IC | Broadcom BCM58202CV3 |
| HDMI Level Shifter | PS8409A |
| USB Hub IC | JHL8040R |
| Power IC(s) | TI TPS65994 |
| Thermal Sensor | SMSC MEC 5200 |
Technical Summary
The Wistron South Peak 15" motherboard, project code 4PD0M6010001 and board number 19819 revision SB, is built around the Intel Tiger Lake-UP3 CPU platform paired with a TGL U PCH-LP southbridge. Graphics are handled by a discrete NVIDIA N18S-G5 GPU with GDDR6 VRAM. The system firmware is stored on a Winbond W25R256JVEIQ 32MB SPI flash in a WSON package, while the SMSC MEC 5200 EC uses a separate Winbond WQ64JVZPIQ 8MB flash ROM. Memory configuration consists of two DDR4x SODIMM slots. The board integrates a Realtek ALC3204 audio codec, a Realtek RTS5242 card reader, an Intel WGI219LM LAN controller, and a Broadcom BCM58202CV3 wireless module. USB-C power delivery and charging are managed by a TI TPS65994 controller, and Thunderbolt 3/USB3.1/DP 1.4 connectivity is provided by an Intel JHL8040R retimer. HDMI output is handled by a PS8409A retimer.
Technician FAQ
Q: What BIOS IC model is used on this motherboard?
A: The BIOS flash is a Winbond W25R256JVEIQ (32MB) in a WSON package.
Q: What EC/KBC chip is used and is it programmable?
A: The EC/KBC is a SMSC MEC 5200. The schematic shows a dedicated Winbond WQ64JVZPIQ (8MB) flash ROM for the EC, indicating it is programmable via SPI.
Q: What is the discrete GPU configuration?
A: The motherboard uses an NVIDIA N18S-G5 GPU with 2GB of GDDR6 VRAM.
Q: What is the charging architecture?
A: USB-C power delivery and charging are controlled by a TI TPS65994 controller.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Attachments
Last edited by a moderator: