hp compaq presario c500 compal ibl30 la-3343p_rev0.1 schematic
hp compaq presario c500=1=compal ibl30 la-3343p_rev0.1.pdf
Technical Specifications
Technical Summary
This Compal LA-3341P revision 0.1 motherboard schematic, dated 2006-05-19, details a Mobile Yonah uFCBGA-479/uFCPGA-478 CPU platform paired with an Intel Calistoga GMCH and ICH7-M southbridge. The graphics architecture supports Intel Calistoga GM/PM+GML configurations. System memory consists of two DDR2 SO-DIMM slots operating in dual-channel mode. The embedded controller is an ENE KB910/L. Audio is handled by an ALC codec, while the LAN controller is a RealTek 8100CL. A thermal sensor ADM1032 is present, and the clock generator is an ICS 954306. The schematic includes a dedicated BIOS section and a DC/DC charging circuit.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is an ENE KB910/L.
Q: What is the LAN IC on this motherboard?
A: The LAN controller is a RealTek 8100CL.
Q: What memory configuration does this motherboard support?
A: It supports two DDR2 SO-DIMM modules in a dual-channel architecture.
Q: What is the clock generator IC on this motherboard?
A: The clock generator is an ICS 954306.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
hp compaq presario c500=1=compal ibl30 la-3343p_rev0.1.pdf
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Compal |
| Motherboard Manufacturer | Compal Electronics, Inc. |
| Board Number | LA-3341P |
| Revision | 0.1 |
| Date | 2006-05-19 |
| CPU Platform | Mobile Yonah uFCBGA-479/uFCPGA-478 CPU |
| PCH / Southbridge | Intel ICH7-M |
| GPU Type | Intel Calistoga GMCH |
| Graphics Architecture | Intel Calistoga GM/PM+GML |
| EC / KBC | ENE KB910/L |
| Audio Codec | ALC |
| BIOS / SPI Flash | BIOS |
| Charging IC | DC/DC |
| RAM Type | DDR2 |
| RAM Architecture | Dual Channel |
| RAM Quantity / Slots | DDR2-SO-DIMM X2 |
| Thermal Sensor | ADM1032 |
| LAN IC | RealTek 8100CL |
| WiFi / WLAN IC | BT Conn |
| Clock Generator | ICS 954306 |
Technical Summary
This Compal LA-3341P revision 0.1 motherboard schematic, dated 2006-05-19, details a Mobile Yonah uFCBGA-479/uFCPGA-478 CPU platform paired with an Intel Calistoga GMCH and ICH7-M southbridge. The graphics architecture supports Intel Calistoga GM/PM+GML configurations. System memory consists of two DDR2 SO-DIMM slots operating in dual-channel mode. The embedded controller is an ENE KB910/L. Audio is handled by an ALC codec, while the LAN controller is a RealTek 8100CL. A thermal sensor ADM1032 is present, and the clock generator is an ICS 954306. The schematic includes a dedicated BIOS section and a DC/DC charging circuit.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is an ENE KB910/L.
Q: What is the LAN IC on this motherboard?
A: The LAN controller is a RealTek 8100CL.
Q: What memory configuration does this motherboard support?
A: It supports two DDR2 SO-DIMM modules in a dual-channel architecture.
Q: What is the clock generator IC on this motherboard?
A: The clock generator is an ICS 954306.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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