hp pavilion dv4 compal_la-4117p_rev0.3 schematic
hp pavilion dv4=1=compal_la-4117p_rev0.3.pdf
Technical Specifications
Technical Summary
This Compal LA-4117P Rev 0.3 schematic, dated 2009-03-15, details a Mobile AMD S1G3 CPU platform with ATI RS880M (NB) and ATI SB710 (SB) core logic. The system BIOS is stored on an MX25L1605AM2C-12G SPI ROM. System management is handled by an ENE KB926-C0 EC/KBC. The audio subsystem features an IDT 9271B7 codec and a TPA6017A2 amplifier. Networking is provided by a Realtek 8102E 10/100M LAN controller. The board supports dual-channel DDR2 800MHz 1.8V memory via two SO-DIMM slots. A JMicron JMB385-LGEZ0A controller manages the card reader interface. Thermal monitoring is performed by an ADM1032ARMZ sensor, and an ST LIS302DLTR accelerometer is present. The clocking solution is a SLG8SP626VTR generator.
Technician FAQ
Q: What BIOS IC model is used on this motherboard?
A: The BIOS SPI flash is an MX25L1605AM2C-12G.
Q: What EC/KBC controller is used on this motherboard?
A: The EC/KBC is an ENE KB926-C0.
Q: What is the memory configuration for this motherboard?
A: The board supports dual-channel DDR2 800MHz 1.8V memory via two DDR2 SO-DIMM slots.
Q: What is the LAN controller on this motherboard?
A: The LAN controller is a Realtek 8102E (10/100M).
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
hp pavilion dv4=1=compal_la-4117p_rev0.3.pdf
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Compal |
| Motherboard Manufacturer | Compal Electronics, Inc. |
| Board Number | LA-4117P |
| Revision | 0.3 |
| Date | 2009-03-15 |
| CPU Platform | Mobile AMD S1G3 CPU |
| GPU Type | ATI RS880M |
| PCH / Southbridge | ATI SB710 |
| EC / KBC | ENE KB926-C0 |
| Audio Codec | IDT 9271B7 |
| BIOS / SPI Flash | MX25L1605AM2C-12G |
| LAN IC | Realtek 8102E |
| Card Reader IC | JMicron JMB385-LGEZ0A |
| Thermal Sensor | ADM1032ARMZ |
| Audio Amplifier | TPA6017A2 |
| Clock Generator | SLG8SP626VTR |
| Accelerometer | ST LIS302DLTR |
| RAM Type | DDR2 800MHz 1.8V |
| RAM Architecture | Dual Channel |
| RAM Quantity / Slots | DDR2-SO-DIMM X2 |
Technical Summary
This Compal LA-4117P Rev 0.3 schematic, dated 2009-03-15, details a Mobile AMD S1G3 CPU platform with ATI RS880M (NB) and ATI SB710 (SB) core logic. The system BIOS is stored on an MX25L1605AM2C-12G SPI ROM. System management is handled by an ENE KB926-C0 EC/KBC. The audio subsystem features an IDT 9271B7 codec and a TPA6017A2 amplifier. Networking is provided by a Realtek 8102E 10/100M LAN controller. The board supports dual-channel DDR2 800MHz 1.8V memory via two SO-DIMM slots. A JMicron JMB385-LGEZ0A controller manages the card reader interface. Thermal monitoring is performed by an ADM1032ARMZ sensor, and an ST LIS302DLTR accelerometer is present. The clocking solution is a SLG8SP626VTR generator.
Technician FAQ
Q: What BIOS IC model is used on this motherboard?
A: The BIOS SPI flash is an MX25L1605AM2C-12G.
Q: What EC/KBC controller is used on this motherboard?
A: The EC/KBC is an ENE KB926-C0.
Q: What is the memory configuration for this motherboard?
A: The board supports dual-channel DDR2 800MHz 1.8V memory via two DDR2 SO-DIMM slots.
Q: What is the LAN controller on this motherboard?
A: The LAN controller is a Realtek 8102E (10/100M).
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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