hp pavilion dv4000 leopard2_rev1 schematic
hp pavilion dv4000=1=leopard2_rev1.pdf
Technical Specifications
Technical Summary
The Wistron Leopard2 motherboard, documented under project code 91.4C701.001 and board number 48.4C701.011, is built around the Dothan Mobile CPU platform with a 400/533MHz Host Bus. The platform utilizes an ICH6-M southbridge and an ATI M26 GPU with a PEG interface. System memory consists of HY5DS573222F-28 DDR-SDRAM modules. The embedded controller is a G768 with 4Mb (512kB) internal flash, and the system BIOS is stored on an LPC Bus Flash ROM. Audio is handled by an AD1981B AC'97 codec, while networking is provided by an RTL8100C 10/100 LAN controller and an 802.11a/b/g Mini-PCI wireless module. Power management is managed by a MAX8725 charger and a suite of DC/DC converters including the MAX1907, MAX8743, and TPS5130. Peripheral connectivity includes a PCI 7411 CardBus/1394 controller and an NS97551 card reader.
Technician FAQ
Q: What is the project code and board number for this motherboard?
A: The project code is 91.4C701.001 and the PCB part number is 48.4C701.011.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is a G768 with 4Mb (512kB) of internal flash memory.
Q: What type of BIOS flash is used?
A: The system uses an LPC Bus Flash ROM for BIOS storage.
Q: What is the charging IC and charger architecture?
A: The charging IC is a MAX8725, and the architecture is a MAXIM CHARGER design.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
hp pavilion dv4000=1=leopard2_rev1.pdf
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Wistron Corporation |
| Model | Leopard2 |
| Motherboard Manufacturer | Wistron Corporation |
| Project Code | 91.4C701.001 |
| Board Number | 48.4C701.011 |
| Revision | 05202 |
| Date | Monday, July 11, 2005 |
| Document Number | A3147 |
| CPU Platform | Dothan Mobile CPU |
| CPU Socket | Host BUS 400/533MHz |
| PCH / Southbridge | ICH6-M |
| GPU Type | ATI M26 |
| Graphics Architecture | PEG |
| EC / KBC | G768 |
| EC/KBC Package | D4Mb(512kB) |
| Audio Codec | AD1981B |
| BIOS / SPI Flash | LPC Bus Flash Rom |
| Charging IC | MAX8725 |
| Charger Architecture | MAXIM CHARGER |
| Power IC(s) | MAX1907, MAX8743, TPS5130, TPS2220, TPS2231 |
| RAM Type | HY5DS573222F-28 |
| RAM Architecture | DDR-SDRAM |
| Card Reader IC | NS97551 |
| LAN IC | RTL8100C |
| WiFi / WLAN IC | 802.11a/b/g Mini-PCI |
| USB Hub IC | PCI 7411 |
Technical Summary
The Wistron Leopard2 motherboard, documented under project code 91.4C701.001 and board number 48.4C701.011, is built around the Dothan Mobile CPU platform with a 400/533MHz Host Bus. The platform utilizes an ICH6-M southbridge and an ATI M26 GPU with a PEG interface. System memory consists of HY5DS573222F-28 DDR-SDRAM modules. The embedded controller is a G768 with 4Mb (512kB) internal flash, and the system BIOS is stored on an LPC Bus Flash ROM. Audio is handled by an AD1981B AC'97 codec, while networking is provided by an RTL8100C 10/100 LAN controller and an 802.11a/b/g Mini-PCI wireless module. Power management is managed by a MAX8725 charger and a suite of DC/DC converters including the MAX1907, MAX8743, and TPS5130. Peripheral connectivity includes a PCI 7411 CardBus/1394 controller and an NS97551 card reader.
Technician FAQ
Q: What is the project code and board number for this motherboard?
A: The project code is 91.4C701.001 and the PCB part number is 48.4C701.011.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is a G768 with 4Mb (512kB) of internal flash memory.
Q: What type of BIOS flash is used?
A: The system uses an LPC Bus Flash ROM for BIOS storage.
Q: What is the charging IC and charger architecture?
A: The charging IC is a MAX8725, and the architecture is a MAXIM CHARGER design.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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