Salim Badakhshan
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Lenovo ThinkPad T14s Gen 2 NM-E091 Rev 1.0 Schematic
Technical Specifications
Technical Summary
The Lenovo T14s Gen2 motherboard, project codes JT4B1 (Phoenix) and JX3B0 (Serval-2), revision 1.0, is built on the Intel Alder Lake P platform with integrated graphics. The system memory architecture uses LPDDR5 at 4800MHz across two channels. The embedded controller is a MEC1723N-L0P-I/LJ in a WQFN56_7X7 package, with a dedicated W25Q80DVUXIET EC flash ROM. The main BIOS SPI flash is a 64MB W25Q512JVEIN. Audio is handled by an ALC3287-CG_MQFN48 HDA codec. The charging controller is a TI TPS65994-AE. Display connectivity includes a Parade-PS8409A HDMI re-timer. The LAN controller is a W8683201, and the wireless module is Garfield Peak -2. The TPM module is an ST33HTPH2X32AHE086. Thunderbolt connectivity is provided by two Burnside Bridge retimers.
Technician FAQ
Q: What BIOS flash IC is used on this motherboard?
A: The main BIOS SPI flash is a W25Q512JVEIN with a capacity of 64MB.
Q: What EC/KBC chip is used and is it programmable?
A: The embedded controller is a MEC1723N-L0P-I/LJ in a WQFN56_7X7 package. The schematic shows a dedicated EC flash ROM (W25Q80DVUXIET), indicating the EC firmware is stored externally and is programmable.
Q: What is the memory architecture of this motherboard?
A: The motherboard uses LPDDR5 memory running at 4800MHz, configured as two channels (Channel A and Channel B).
Q: What is the charging controller on this board?
A: The charging controller is a TI TPS65994-AE, which also functions as a PD controller.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Lenovo |
| Model | T14s Gen2 |
| Project Code | JT4B1(Phoenix) / JX3B0 (Serval-2) |
| Revision | 1.0 |
| Date | Tuesday, January 04, 2022 |
| CPU Platform | Intel Alder Lake P 6C+8C |
| EC / KBC | MEC1723N-L0P-I/LJ |
| EC/KBC Package | WQFN56_7X7 |
| Audio Codec | ALC3287-CG_MQFN48 |
| BIOS / SPI Flash | W25Q512JVEIN |
| BIOS Flash Capacity | 64MB |
| EC Flash / ROM | W25Q80DVUXIET |
| Charging IC | TI TPS65994-AE |
| RAM Type | LPDDR5 |
| RAM Architecture | LPDDR5 4800MHz Channel A / Channel B |
| LAN IC | W8683201 |
| WiFi / WLAN IC | Garfield Peak -2 |
| HDMI Level Shifter | Parade-PS8409A |
| Card Reader IC | D518FTG |
| USB Hub IC | TBT Retimer Burnside Bridge CH1 / CH2 |
| TPM | ST33HTPH2X32AHE086 |
| GPU Type | Integrated (Alder Lake P) |
Technical Summary
The Lenovo T14s Gen2 motherboard, project codes JT4B1 (Phoenix) and JX3B0 (Serval-2), revision 1.0, is built on the Intel Alder Lake P platform with integrated graphics. The system memory architecture uses LPDDR5 at 4800MHz across two channels. The embedded controller is a MEC1723N-L0P-I/LJ in a WQFN56_7X7 package, with a dedicated W25Q80DVUXIET EC flash ROM. The main BIOS SPI flash is a 64MB W25Q512JVEIN. Audio is handled by an ALC3287-CG_MQFN48 HDA codec. The charging controller is a TI TPS65994-AE. Display connectivity includes a Parade-PS8409A HDMI re-timer. The LAN controller is a W8683201, and the wireless module is Garfield Peak -2. The TPM module is an ST33HTPH2X32AHE086. Thunderbolt connectivity is provided by two Burnside Bridge retimers.
Technician FAQ
Q: What BIOS flash IC is used on this motherboard?
A: The main BIOS SPI flash is a W25Q512JVEIN with a capacity of 64MB.
Q: What EC/KBC chip is used and is it programmable?
A: The embedded controller is a MEC1723N-L0P-I/LJ in a WQFN56_7X7 package. The schematic shows a dedicated EC flash ROM (W25Q80DVUXIET), indicating the EC firmware is stored externally and is programmable.
Q: What is the memory architecture of this motherboard?
A: The motherboard uses LPDDR5 memory running at 4800MHz, configured as two channels (Channel A and Channel B).
Q: What is the charging controller on this board?
A: The charging controller is a TI TPS65994-AE, which also functions as a PD controller.
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