Salim Badakhshan
Registered
Lenovo Thinkpad X13-T14s Gen 1 Intel GT4A3-GX3A2 NM-C891 Rev 1.0 Schematic
Technical Specifications
Technical Summary
This LC Future Center schematic, revision VER 1.0 dated Aug/8/2019, documents the Jazz2/Sideswipe2 project for the T14S/X13 platform. The motherboard utilizes a DDR4 memory architecture with four sub-channels (A, B, C, D). The embedded controller is a MEC1663, and the audio subsystem is built around an ALC3287 codec. Power management includes a BQ25700A battery charger and a comprehensive set of DC/DC converters and load switches, including the NB690, NB693, TPS51393, BU90104, MP2949AGQKT, MP86901C, MP86901, MP86901A, and NB687. The system integrates a GBE JACKSONVILLE LAN controller, a MEDIA CARD CONTROLLER, a DDI DEMUX/HDMI LEVEL SHIFTE, a USB PD CONTROLLER, and a CNVI interface for wireless connectivity. Security is handled by a discrete TPM 2.0 module, and an APS G-SENSOR is present for thermal management.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is a MEC1663.
Q: What is the charging IC and architecture?
A: The battery charger IC is a BQ25700A.
Q: What audio codec is present?
A: The audio codec is an ALC3287.
Q: What is the memory architecture?
A: The motherboard uses DDR4 memory configured across four sub-channels: SUB CHANNEL-A, SUB CHANNEL-B, SUB CHANNEL-C, and SUB CHANNEL-D.
Q: What is the project code and platform?
A: The project code is Jazz2/Sideswipe2, and the platform is T14S/X13.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | LC Future Center |
| Project Code | Jazz2/Sideswipe2 |
| Revision | VER 1.0 |
| Date | Aug/8/2019 |
| CPU Platform | T14S/X13 |
| Charger Architecture | BQ25700A |
| Audio Codec | ALC3287 |
| EC / KBC | MEC1663 |
| RAM Type | DDR4 |
| RAM Architecture | SUB CHANNEL-A, SUB CHANNEL-B, SUB CHANNEL-C, SUB CHANNEL-D |
| LAN IC | GBE JACKSONVILLE |
| Card Reader IC | MEDIA CARD CONTROLLER |
| HDMI Level Shifter | DDI DEMUX/HDMI LEVEL SHIFTE |
| USB Hub IC | USB PD CONTROLLER |
| WiFi / WLAN IC | CNVI |
| Power IC(s) | NB690, NB693, TPS51393, BU90104, MP2949AGQKT, MP86901C, MP86901, MP86901A, NB687 |
| Charging IC | BQ25700A |
| Thermal Sensor | APS G-SENSOR |
| TPM | DISCRETE TPM 2.0 |
Technical Summary
This LC Future Center schematic, revision VER 1.0 dated Aug/8/2019, documents the Jazz2/Sideswipe2 project for the T14S/X13 platform. The motherboard utilizes a DDR4 memory architecture with four sub-channels (A, B, C, D). The embedded controller is a MEC1663, and the audio subsystem is built around an ALC3287 codec. Power management includes a BQ25700A battery charger and a comprehensive set of DC/DC converters and load switches, including the NB690, NB693, TPS51393, BU90104, MP2949AGQKT, MP86901C, MP86901, MP86901A, and NB687. The system integrates a GBE JACKSONVILLE LAN controller, a MEDIA CARD CONTROLLER, a DDI DEMUX/HDMI LEVEL SHIFTE, a USB PD CONTROLLER, and a CNVI interface for wireless connectivity. Security is handled by a discrete TPM 2.0 module, and an APS G-SENSOR is present for thermal management.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is a MEC1663.
Q: What is the charging IC and architecture?
A: The battery charger IC is a BQ25700A.
Q: What audio codec is present?
A: The audio codec is an ALC3287.
Q: What is the memory architecture?
A: The motherboard uses DDR4 memory configured across four sub-channels: SUB CHANNEL-A, SUB CHANNEL-B, SUB CHANNEL-C, and SUB CHANNEL-D.
Q: What is the project code and platform?
A: The project code is Jazz2/Sideswipe2, and the platform is T14S/X13.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Attachments
Last edited by a moderator:
