Microsoft Surface Pro 8 Catania MB Schematic
Technical Specifications
Technical Summary
The CATANIA JDM1 project is a Tiger Lake UP3 platform motherboard dated January 6, 2021, revision 1.1. The system is managed by a NUVOTON NPCT750SABYX EC/KBC with firmware version 7.2.1.032KBEEPROM, and features a WINBOND W25R256JWPI 256Mb SPI ROM for BIOS storage. Memory architecture consists of LPDDR4X x32 memory down configuration with two channels, each using
Technical Specifications
Technical Summary
The XDM CATANIA JDM1 revision 1.1 motherboard is built on the Intel Tiger Lake UP3 platform. The system firmware is stored on a 256Mb WINBOND W25R256JWPI SPI ROM, while the NUVOTON NPCT750SABYX EC/KBC has a dedicated 16Mb WINBOND W25Q16FWUXIE SPI flash. Memory architecture consists of LPDDR4X memory down, configured as two 32-bit channels each using two x32 packages. Audio is handled by a REALTEK ALC3300 codec, and charging is managed by a TI BQ25713 battery charger. The board integrates an Intel HrP21216 Type CNVi module for WLAN and Bluetooth connectivity, and uses TI TPS65994 for USB-C power delivery control.
Technician FAQ
Q: What BIOS IC model is used on this motherboard?
A: The BIOS SPI ROM is a WINBOND W25R256JWPI with a capacity of 256Mb.
Q: Is the EC/KBC programmable on this motherboard?
A: Yes, the NUVOTON NPCT750SABYX EC/KBC has a dedicated 16Mb WINBOND W25Q16FWUXIE SPI flash for firmware.
Q: What is the memory architecture of this motherboard?
A: The board uses LPDDR4X memory down configuration with two 32-bit channels, each populated with two x32 memory packages.
Q: What charging IC is used on this motherboard?
A: The battery charger IC is a TI BQ25713.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Project Name | CATANIA |
| Project Code | JDM1 |
| Revision | 1.1 |
| Date | Wednesday, January 06, 2021 |
| CPU Platform | Tiger Lake UP3 |
| EC / KBC | NUVOTON/NPCT750SABYX |
| EC/KBC Programmable | FW:7.2.1.032KBEEPROM |
| Audio Codec | REALTEK/ALC3300 |
| BIOS / SPI Flash | WINBOND/W25R256JWPI |
| BIOS Flash Capacity | 256Mb SPI ROM |
| EC Flash / ROM | WINBOND/W25Q16FWUXIE 16Mb SPI Flash |
| Charging IC | TI/BQ25713 |
| Charger Architecture | BATT Charger |
| Power IC(s) | DIALOG/SLG4U43532VTR |
| RAM Type | LPDDR4X x32 |
| RAM Architecture | Channel A, 32bit x2 LPDDR4X x32 2pcs; Channel B, 32bit x2 LPDDR4X x32 2pcs |
| RAM Quantity / Slots | Memory Down |
| Thermal Sensor | TI/SN1608035DRL |
| Card Reader IC | REALTEK/ALC1304M |
| USB Hub IC | NXP/RT600 |
| LAN IC | Intel HrP2 1216 Type CNVi WLAN + BT |
| WiFi / WLAN IC | Intel HrP2 1216 Type CNVi WLAN + BT |
| HDMI Level Shifter | Re-Timer |
| GPU Type | Integrated |
| Graphics Architecture | Tiger Lake UP3 |
| PCH / Southbridge | Intel Tiger Lake UP3 |
| Audio Amplifier | REALTEK/ALC1304M |
| USB-C Controller | TI/TPS65994 |
| PD Controller | TI/TPS65994 |
| Sensor | BOSCH/BMA253 (optional) |
| Sensor | BOSCH/BMI260 |
| Sensor | AMS/TCS34303 |
| Sensor | MEMSIC/MMC3630KJ |
| Hall Sensor | ROHM/BU52058GWZ-E2 |
| Security Device | ST33J2M0 |
| eSIM | AAC/SDM0502B-RS261-M02 |
| TPM | ST33J2M0 |
| Silego Controller | DIALOG/SLG4U43532VTR |
Technical Summary
The CATANIA JDM1 project is a Tiger Lake UP3 platform motherboard dated January 6, 2021, revision 1.1. The system is managed by a NUVOTON NPCT750SABYX EC/KBC with firmware version 7.2.1.032KBEEPROM, and features a WINBOND W25R256JWPI 256Mb SPI ROM for BIOS storage. Memory architecture consists of LPDDR4X x32 memory down configuration with two channels, each using
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | XDM |
| Model | CATANIA |
| Project Code | CATANIA |
| Revision | 1.1 |
| Date | Wednesday, January 06, 2021 |
| CPU Platform | Tiger Lake UP3 |
| EC / KBC | NUVOTON/NPCT750SABYX |
| Audio Codec | REALTEK/ALC3300 |
| BIOS / SPI Flash | WINBOND/W25R256JWPI |
| BIOS Flash Capacity | 256Mb |
| EC Flash / ROM | WINBOND/W25Q16FWUXIE |
| EC Flash / ROM Capacity | 16Mb |
| Charging IC | TI/BQ25713 |
| Charger Architecture | BATT Charger |
| RAM Type | LPDDR4X |
| RAM Architecture | Channel A, 32bit x2 LPDDR4X x32 2pcs; Channel B, 32bit x2 LPDDR4X x32 2pcs |
| Card Reader IC | REALTEK/RT600 |
| USB Hub IC | DIALOG/SLG4U43532VTR |
| LAN IC | Intel HrP21216 Type CNVi WLAN + BT |
| WiFi / WLAN IC | Intel HrP21216 Type CNVi WLAN + BT |
| HDMI Level Shifter | AAC/SDM0502B-RS261-M02 |
| Thermal Sensor | TI/SN1608035DRLR |
| Power IC(s) | TI/TPS65994 |
| RAM Quantity / Slots | Memory Down |
Technical Summary
The XDM CATANIA JDM1 revision 1.1 motherboard is built on the Intel Tiger Lake UP3 platform. The system firmware is stored on a 256Mb WINBOND W25R256JWPI SPI ROM, while the NUVOTON NPCT750SABYX EC/KBC has a dedicated 16Mb WINBOND W25Q16FWUXIE SPI flash. Memory architecture consists of LPDDR4X memory down, configured as two 32-bit channels each using two x32 packages. Audio is handled by a REALTEK ALC3300 codec, and charging is managed by a TI BQ25713 battery charger. The board integrates an Intel HrP21216 Type CNVi module for WLAN and Bluetooth connectivity, and uses TI TPS65994 for USB-C power delivery control.
Technician FAQ
Q: What BIOS IC model is used on this motherboard?
A: The BIOS SPI ROM is a WINBOND W25R256JWPI with a capacity of 256Mb.
Q: Is the EC/KBC programmable on this motherboard?
A: Yes, the NUVOTON NPCT750SABYX EC/KBC has a dedicated 16Mb WINBOND W25Q16FWUXIE SPI flash for firmware.
Q: What is the memory architecture of this motherboard?
A: The board uses LPDDR4X memory down configuration with two 32-bit channels, each populated with two x32 memory packages.
Q: What charging IC is used on this motherboard?
A: The battery charger IC is a TI BQ25713.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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