toshiba nb520 compal_la-6859p_rev1.0 schematic
toshiba nb520=1=compal_la-6859p_rev1.0.pdf
Technical Specifications
Technical Summary
This Compal LA-6859P REV:1.0 schematic, dated 2011-11-07, documents the Cougar 2.0 platform built around an Intel Cedar Trail Processor featuring an Intel Cedarview 2 Core 1.86GHz (6.5W) CPU paired with a Tiger Point PCH. The system uses an ENE KB930 E0 EC/KBC and an ALC269 HDA codec. The main BIOS is stored on a 2MB SPI ROM, while the EC firmware resides on a separate 128KB SPI ROM. Memory configuration consists of DDRIII-SO-DIMM running at 1.5V DDRIII 1066MHz. Networking is handled by an RTL8105E 10/100 LAN controller, and the card reader interface uses an RTL5137 IC. The clock generation is managed by an RTM890N-397 low power clock generator.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The EC/KBC is an ENE KB930 E0.
Q: What are the BIOS and EC flash configurations?
A: The main BIOS is a 2MB SPI ROM, and the EC firmware is stored on a separate 128KB SPI ROM.
Q: What is the memory architecture?
A: The board uses DDRIII-SO-DIMM modules running at 1.5V DDRIII 1066MHz.
Q: What LAN and card reader controllers are present?
A: The LAN controller is an RTL8105E 10/100, and the card reader controller is an RTL5137.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
toshiba nb520=1=compal_la-6859p_rev1.0.pdf
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Compal |
| Motherboard Manufacturer | Compal Electronics, Inc. |
| Project Code | QBU00 |
| Board Number | LA-6859P |
| Revision | REV:1.0 |
| Date | 2011-11-07 |
| Document Number | 4019EGBSCHEAMTIC A6859 |
| CPU Platform | Intel Cedar Trail Processor |
| Platform Alias | Cougar 2.0 |
| CPU Model | Intel Cedarview 2 Core 1.86GHz (6.5W) |
| PCH / Southbridge | Tiger Point |
| EC / KBC | ENE KB930 E0 |
| Audio Codec | ALC269 |
| BIOS / SPI Flash | SPI ROM 2MB |
| EC Flash / ROM | SPI ROM 128KB |
| RAM Type | DDRIII-SO-DIMM |
| RAM Architecture | 1.5V DDRIII 1066MHz |
| LAN IC | RTL8105E 10/100 LAN |
| Card Reader IC | RTL5137 |
| Clock Generator | RTM890N-397 |
Technical Summary
This Compal LA-6859P REV:1.0 schematic, dated 2011-11-07, documents the Cougar 2.0 platform built around an Intel Cedar Trail Processor featuring an Intel Cedarview 2 Core 1.86GHz (6.5W) CPU paired with a Tiger Point PCH. The system uses an ENE KB930 E0 EC/KBC and an ALC269 HDA codec. The main BIOS is stored on a 2MB SPI ROM, while the EC firmware resides on a separate 128KB SPI ROM. Memory configuration consists of DDRIII-SO-DIMM running at 1.5V DDRIII 1066MHz. Networking is handled by an RTL8105E 10/100 LAN controller, and the card reader interface uses an RTL5137 IC. The clock generation is managed by an RTM890N-397 low power clock generator.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The EC/KBC is an ENE KB930 E0.
Q: What are the BIOS and EC flash configurations?
A: The main BIOS is a 2MB SPI ROM, and the EC firmware is stored on a separate 128KB SPI ROM.
Q: What is the memory architecture?
A: The board uses DDRIII-SO-DIMM modules running at 1.5V DDRIII 1066MHz.
Q: What LAN and card reader controllers are present?
A: The LAN controller is an RTL8105E 10/100, and the card reader controller is an RTL5137.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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