XPS 13 9360 LA-F051P
Technical Specifications
Technical Summary
This Dell Compal LA-F051P (CAZ70) motherboard, revision 1.0 (A00) dated 2017-09-21, is built on the Kaby Lake R 4+2 ULT platform. The system uses a 256Mb SPI ROM for BIOS storage and is managed by an MEC 5085 EC/KBC, which is programmable. Audio is handled by an ALC3246 codec, while the charging architecture is controlled by a TPS65982 PD controller. Memory architecture consists of dual-channel non-interleave LPDDR3. Peripheral connectivity includes an RTS5242D card reader, a USB5742 USB hub, an ECE1117BK LAN controller, and WLAN BT 4.0. The HDMI interface is managed via an Alpine Ridge Thunderbolt level shifter.
Technician FAQ
Q: What is the BIOS flash configuration on this motherboard?
A: The motherboard uses a 256Mb SPI ROM for BIOS storage.
Q: Is the EC/KBC programmable on this motherboard?
A: Yes, the MEC 5085 EC/KBC is programmable.
Q: What is the charging IC used on this motherboard?
A: The charging IC is a TPS65982 PD controller.
Q: What is the memory architecture of this motherboard?
A: The memory architecture is dual-channel non-interleave LPDDR3.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Dell |
| Motherboard Manufacturer | Compal |
| Model Name | LA-F051P |
| Project Code | Dino-R (Kaby Lake ULT) |
| Board Number | CAZ70 |
| Revision | 1.0 (A00) |
| Date | 2017-09-21 |
| Document Number | DAA000E0010 |
| CPU Platform | Kaby Lake R 4+2 ULT |
| EC / KBC | MEC 5085 |
| EC/KBC Programmable | Yes |
| Audio Codec | ALC3246 |
| BIOS / SPI Flash | SPI ROM 256Mb |
| Charging IC | TPS65982 |
| RAM Type | LPDDR3 |
| RAM Architecture | Dual Channel Non-Interleave |
| Card Reader IC | RTS5242D |
| USB Hub IC | USB5742 |
| LAN IC | ECE1117BK |
| WiFi / WLAN IC | WLAN BT 4.0 |
| HDMI Level Shifter | Alpine Ridge Thunderbolt |
Technical Summary
This Dell Compal LA-F051P (CAZ70) motherboard, revision 1.0 (A00) dated 2017-09-21, is built on the Kaby Lake R 4+2 ULT platform. The system uses a 256Mb SPI ROM for BIOS storage and is managed by an MEC 5085 EC/KBC, which is programmable. Audio is handled by an ALC3246 codec, while the charging architecture is controlled by a TPS65982 PD controller. Memory architecture consists of dual-channel non-interleave LPDDR3. Peripheral connectivity includes an RTS5242D card reader, a USB5742 USB hub, an ECE1117BK LAN controller, and WLAN BT 4.0. The HDMI interface is managed via an Alpine Ridge Thunderbolt level shifter.
Technician FAQ
Q: What is the BIOS flash configuration on this motherboard?
A: The motherboard uses a 256Mb SPI ROM for BIOS storage.
Q: Is the EC/KBC programmable on this motherboard?
A: Yes, the MEC 5085 EC/KBC is programmable.
Q: What is the charging IC used on this motherboard?
A: The charging IC is a TPS65982 PD controller.
Q: What is the memory architecture of this motherboard?
A: The memory architecture is dual-channel non-interleave LPDDR3.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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