acer aspire e5-575 quanta zaa x16
Technical Specifications
Technical Summary
This Quanta ZAA project, document number 1A148 revision 1A dated February 5, 2016, is based on the SKY LAKE ULT 15W platform with integrated PCH. The system block diagram indicates a dual-channel DDR4 memory architecture with two SODIMM slots. Graphics are handled by an integrated GT3e iGPU. The embedded controller is an IT8987, and the audio codec is an ALC255. The SPI ROM configuration is 8M+4M. Power management includes a BQ24780S battery charger, a TPS51225R regulator, and an ISL95859HRTZ-T VR controller. The system integrates an RTL8411 combo card reader and LAN IC, a PTN3366B HDMI level shifter, and a TPS25810 USB hub IC. The block diagram also notes support for a G-SENSOR thermal sensor and WLAN+BT wireless connectivity.
Technician FAQ
Q: What is the SPI ROM configuration on this motherboard?
A: The SPI ROM is configured as 8M+4M.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is an IT8987.
Q: What is the charging IC and architecture?
A: The charging IC is a BQ24780S, and the architecture is a battery charger.
Q: What is the memory architecture?
A: The memory architecture is dual-channel DDR4 with two SODIMM slots.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Quanta Computer Inc. |
| Project Code | ZAA |
| Document Number | 1A148 |
| Revision | 1A |
| Date | Friday, February 05, 2016 |
| CPU Platform | SKY LAKE ULT 15W |
| Platform Alias | SKL ULT |
| GPU Type | iGPU |
| Graphics Architecture | GT3e |
| EC / KBC | IT8987 |
| Audio Codec | ALC255 |
| BIOS / SPI Flash | SPI ROM 8M+4M |
| Charging IC | BQ24780S |
| Power IC(s) | TPS51225R, ISL95859HRTZ-T, RT8237CZQW, RT8068AZQW, ISL95808 |
| RAM Type | DDR4 |
| RAM Architecture | Dual Channel DDR4 |
| RAM Quantity / Slots | 2 |
| Card Reader IC | RTL8411 |
| LAN IC | RTL8411 |
| HDMI Level Shifter | PTN3366B |
| WiFi / WLAN IC | WLAN+BT |
| USB Hub IC | TPS25810 |
| Charger Architecture | Batery Charger |
| Thermal Sensor | G-SENSOR |
Technical Summary
This Quanta ZAA project, document number 1A148 revision 1A dated February 5, 2016, is based on the SKY LAKE ULT 15W platform with integrated PCH. The system block diagram indicates a dual-channel DDR4 memory architecture with two SODIMM slots. Graphics are handled by an integrated GT3e iGPU. The embedded controller is an IT8987, and the audio codec is an ALC255. The SPI ROM configuration is 8M+4M. Power management includes a BQ24780S battery charger, a TPS51225R regulator, and an ISL95859HRTZ-T VR controller. The system integrates an RTL8411 combo card reader and LAN IC, a PTN3366B HDMI level shifter, and a TPS25810 USB hub IC. The block diagram also notes support for a G-SENSOR thermal sensor and WLAN+BT wireless connectivity.
Technician FAQ
Q: What is the SPI ROM configuration on this motherboard?
A: The SPI ROM is configured as 8M+4M.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is an IT8987.
Q: What is the charging IC and architecture?
A: The charging IC is a BQ24780S, and the architecture is a battery charger.
Q: What is the memory architecture?
A: The memory architecture is dual-channel DDR4 with two SODIMM slots.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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