Salim Badakhshan
Registered
Benq Quanta S72 Schematic
Technical Specifications
Technical Summary
This Quanta Computer Inc. motherboard, project code S73_BRIDGE, is documented with a revision date of Friday, April 23, 2004. The schematic includes revision history noting a preliminary release on 04/08/2004 and an update on 04/23/2004 to add two P3V3 pins on U1. The board features a 40-pin connector interface with signals including PCI Express lanes, SMBus, and power rails such as P1V5, P12V, P5V, P3V3, and P3V3_STB.
Technician FAQ
Q: What is the project code for this motherboard?
A: The project code is S73_BRIDGE.
Q: What is the revision history of this schematic?
A: The schematic has Rev A(04/08/2004) for preliminary release and Rev A(04/23/2004) which added two P3V3 pins on U1.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
Technical Summary
This Quanta Computer Inc. S73 PCI_BASE project motherboard, documented under revision A dated Monday, May 17, 2004, is a PCI riser card platform. The embedded controller is an MEC8-80PDFHS80FR0251, and the EC flash/ROM is provided by an AT24C02A EEPROM. The board includes SCSI Gold Finger connectors and PCI Express expansion slots, with SMBus bridge signals for system management.
Technician FAQ
Q: What EC/KBC chip is used on this motherboard?
A: The embedded controller is an MEC8-80PDFHS80FR0251.
Q: What EC flash/ROM chip is used?
A: The EC flash/ROM is an AT24C02A EEPROM.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
Technical Summary
This Quanta Computer Inc. document, project code S73_PCI_RISER, revision 1A, dated Friday, April 23, 2004, details a PCI Riser board design. The schematic includes a PCI Connector (J1) and two MEC1 78-pin connectors (J2, J3) for connection to a PCI Base Board. The document number is Custom13.
Technician FAQ
Q: What is the project code for this PCI riser board?
A: The project code is S73_PCI_RISER.
Q: What is the document revision and date?
A: The document revision is 1A, dated Friday, April 23, 2004.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
Technical Summary
The Quanta S27 project motherboard is designed for the LGA775 socket, supporting Prescott, Smithfield, and Cedar Mill processors. The platform is built around the Mukilteo MCH northbridge paired with the ICH7R southbridge, connected via DMI. Memory architecture consists of un-buffered DDR-2 across four DIMM slots, supporting dual-channel configurations up to 8GB. The system utilizes a FWH BIOS for firmware storage. The Super I/O and EC/KBC functions are handled by the NS PC8374K. Networking is provided by dual BCM5721J LAN controllers. Graphics are driven by an XG20 VGA controller. Clock generation is managed by the ICS954201 CK410 clock generator. System management is handled by a BMC_H8 controller with dedicated SRAM, flash, and temperature sensor, alongside a BMC CPLD. Power regulation includes a CPU Voltage Regulator compliant with VRD 10.1 and a dedicated DRAM Voltage Regulator.
Technician FAQ
Q: What is the project code and board number for this motherboard?
A: The project code is S27, manufactured by Quanta Computer INC.
Q: What CPU socket and platform does this motherboard support?
A: It supports the LGA775 socket for Prescott, Smithfield, and Cedar Mill processors.
Q: What type of BIOS is used on this motherboard?
A: The motherboard uses a FWH BIOS for firmware storage.
Q: What is the memory architecture of this motherboard?
A: It supports un-buffered DDR-2 memory in a dual-channel configuration across four DIMM slots, with a maximum capacity of 8GB.
Q: What EC/KBC and Super I/O controller is used?
A: The NS PC8374K serves as both
Technical Specifications
Technical Summary
This Quanta Computer Inc. S73 PCI_BASE project motherboard, documented under revision A dated Monday, May 17, 2004, utilizes a MEC8-80PDFHS80FR0251 embedded controller in an 80-pin package. The EC firmware is supported by an AT24C02A serial EEPROM. The board integrates a PCI riser card slot and a SCSI gold finger connector, with power rails including P3V3, P5V, P12V, P1V5, and P3V3_STB. The design incorporates a PXA processor interface and an Intel PXH controller for PCI-X and PCI Express connectivity, with SMBus lines for system management.
Technician FAQ
Q: What EC/KBC chip is used on this motherboard?
A: The motherboard uses a MEC8-80PDFHS80FR0251 embedded controller in an 80-pin package.
Q: What EC flash/ROM device is used?
A: The EC firmware is stored on an AT24C02A serial EEPROM.
Q: What is the project code and document number for this board?
A: The project code is S73 PCI_BASE, and the document number is C8, revision A, dated May 17, 2004.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
Technical Summary
The BenQ DH7000 (JOYBOOK S72) motherboard, documented under project code 99.K1201.001 and board number 99.K1201.002, is built around the Intel Dothan processor platform with an Intel 915PM chipset and ICH6-M (82801FM) southbridge. Graphics are handled by an ATI M24P controller. The system uses an SMSC LPC47N249 EC/KBC and an ADI1980 audio codec. Networking is provided by Realtek RTL8100CL and RTL8110SB(L) LAN ICs, with Intel PRO/Wireless 2915ABG or 2200BG WLAN adapters. Memory configuration includes two DDR 333 slots supporting up to 2GB. The TI PCI7411 controller manages the 4-in-1 card reader.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The motherboard uses an SMSC LPC47N249 EC/KBC.
Q: What audio codec is used on this motherboard?
A: The audio codec is an ADI1980.
Q: What LAN ICs are used on this motherboard?
A: The motherboard uses Realtek RTL8100CL and Realtek RTL8110SB(L) LAN ICs.
Q: What memory type and configuration does this motherboard support?
A: The motherboard supports DDR 333 memory with 2 slots, expandable to a maximum of 2GB.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
Technical Summary
This motherboard schematic, dated Friday, May 21, 2004, is built around the Lindenhurst CPU platform with an ICH5R southbridge. The system employs a dual CPU configuration (CPU0 and CPU1) with dedicated VRD controllers (VRD 0 and VRD 1) providing P_VCCP0 and P_VCCP1 power rails. Power sequencing includes VID_PWRGD, CPU_VRD_PWRGD, and SYS_PWRGD signals with specified delays. The board utilizes an SIO PC87373 Super I/O for legacy I/O management and includes SLP_S3_N and SLP_S5_N sleep state signals. Memory architecture supports DDR with separate DDR A and DDR B reset signals (DDRA_RESET_N and DDRB_RESET_N). The schematic also documents the H8_PWBTN_IN_N power button input and PS_ON_PWR_N control signals.
Technician FAQ
Q: What is the CPU platform and southbridge used on this motherboard?
A: The CPU platform is Lindenhurst and the southbridge is ICH5R.
Q: What Super I/O controller is used?
A: The Super I/O controller is SIO PC87373.
Q: What is the document date of this schematic?
A: The schematic is dated Friday, May 21, 2004.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
Technical Summary
This motherboard schematic, dated Friday, May 21, 2004, is built around the Intel ICH5R southbridge. The platform architecture includes CPU0 and CPU1 support, with a VGA component present. The reset and power sequencing involves signals such as SIO_PCIRST_N, SB_CPURST_N, PCI32_PCIRST_N, and RSM RST_N, with the ICH5R requiring VRMPWRGD and PWOK to be ready. The H8 EC/KBC and BIOS are also referenced in the power and reset distribution.
Technician FAQ
Q: What southbridge is used on this motherboard?
A: The Intel ICH5R southbridge is used.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Quanta Computer Inc. |
| Project Code | S73_BRIDGE |
| Date | Friday, April 23, 2004 |
| Revision | Rev A(04/23/2004) |
Technical Summary
This Quanta Computer Inc. motherboard, project code S73_BRIDGE, is documented with a revision date of Friday, April 23, 2004. The schematic includes revision history noting a preliminary release on 04/08/2004 and an update on 04/23/2004 to add two P3V3 pins on U1. The board features a 40-pin connector interface with signals including PCI Express lanes, SMBus, and power rails such as P1V5, P12V, P5V, P3V3, and P3V3_STB.
Technician FAQ
Q: What is the project code for this motherboard?
A: The project code is S73_BRIDGE.
Q: What is the revision history of this schematic?
A: The schematic has Rev A(04/08/2004) for preliminary release and Rev A(04/23/2004) which added two P3V3 pins on U1.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Quanta Computer Inc. |
| Project Code | S73 PCI_BASE |
| Document Number | C820.01UF10%50V+CE2100UF20%10V12C870.01UF10%50VC900.1UF10%25V+CE1100UF20%10V12C880.01UF10%50VC8910UF20%16VC910.1UF20%25VH3C7-5D4-3_BMMBS72002014HOLE_C7-5D4-3_BMR642.7K5%J2SCSI_Gold_FingerGOLD_SCSI78P113355779911111313151517171919212123232525272729293333353537373939414143434545474749495151535355555757595961616363656567672244668810101212141416161818202022222424262628283030343436363838404042424444464648485050525254545656585860606262646466666868696971717373757577777979707072727474767678788080C830.1UF20%25VTP2081C920.1UF20%25VH4C7-5D4-3_BMMBS72002014HOLE_C7-5D4-3_BMR652.7K5%TP2061C840.1UF20%25VH5C7-5D4-3_BMMBS72002014HOLE_C7-5D4-3_BMC930.01UF10%50VTP2071Quanta Computer Inc.PROJECT : S73_PCI_BASER661005%C9510UF20%16VJ1SCSI_Gold_FingerGOLD_SCSI78P113355779911111313151517171919212123232525272729293333353537373939414143434545474749495151535355555757595961616363656567672244668810101212141416161818202022222424262628283030343436363838404042424444464648485050525254545656585860606262646466666868696971717373757577777979707072727474767678788080C850.1UF20%25VH6C7-5D4-3_BMMBS72002014HOLE_C7-5D4-3_BMC940.01UF10%50VC960.1UF10%25VC860.01UF10%50V |
| Revision | A |
| Date | Monday, May 17, 2004 |
| EC / KBC | MEC8-80PDFHS80FR0251 |
| EC/KBC Package | 11335577991111131315151717191921212323252527272929313133333535373739394141434345454747494951515353555557575959616163636565676769697171737375757777797922446688101012121414161618182020222224242626282830303232343436363838404042424444464648485050525254545656585860606262646466666868707072727474767678788080 |
| EC Flash / ROM | AT24C02A |
Technical Summary
This Quanta Computer Inc. S73 PCI_BASE project motherboard, documented under revision A dated Monday, May 17, 2004, is a PCI riser card platform. The embedded controller is an MEC8-80PDFHS80FR0251, and the EC flash/ROM is provided by an AT24C02A EEPROM. The board includes SCSI Gold Finger connectors and PCI Express expansion slots, with SMBus bridge signals for system management.
Technician FAQ
Q: What EC/KBC chip is used on this motherboard?
A: The embedded controller is an MEC8-80PDFHS80FR0251.
Q: What EC flash/ROM chip is used?
A: The EC flash/ROM is an AT24C02A EEPROM.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Quanta Computer Inc. |
| Project Code | S73_PCI_RISER |
| Date | Friday, April 23, 2004 |
| Document Number | Custom13 |
| Revision | 1A |
Technical Summary
This Quanta Computer Inc. document, project code S73_PCI_RISER, revision 1A, dated Friday, April 23, 2004, details a PCI Riser board design. The schematic includes a PCI Connector (J1) and two MEC1 78-pin connectors (J2, J3) for connection to a PCI Base Board. The document number is Custom13.
Technician FAQ
Q: What is the project code for this PCI riser board?
A: The project code is S73_PCI_RISER.
Q: What is the document revision and date?
A: The document revision is 1A, dated Friday, April 23, 2004.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Quanta Computer INC. |
| Project | S27 |
| Date | Monday, March 21, 2005 |
| CPU Platform | Prescott / Smithfield / Cedar Mill LGA775 |
| CPU Socket | LGA775 |
| PCH / Southbridge | |
| MCH / Northbridge | Mukilteo MCH |
| Southbridge | ICH7R |
| GPU Type | XG20 |
| EC / KBC | PC8374K |
| Super I/O | NS PC8374K |
| BIOS / SPI Flash | FWH BIOS |
| RAM Type | Un-buffered DDR-2 |
| RAM Architecture | 8GB Dual Channel 4 DIMMs |
| RAM Quantity / Slots | 4 DIMMs |
| LAN IC | BCM5721J |
| Clock Generator | ICS954201 CK410 |
| BMC | BMC_H8 |
| BMC SRAM | BMC SRAM, FLASH, TEMPSENSOR |
| BMC CPLD | BMC CPLD |
| VGA | XG20 |
| Charger Architecture | Power Connectors |
| Power IC(s) | CPU Voltage Regulator VRD 10.1, DRAM Voltage Regulator |
| Thermal Sensor | TEMPSENSOR |
| Card Reader IC | Not explicitly present in source |
| USB Hub IC | Not explicitly present in source |
| WiFi / WLAN IC | Not explicitly present in source |
| HDMI Level Shifter | Not explicitly present in source |
| Audio Codec | Not explicitly present in source |
| Charging IC | Not explicitly present in source |
Technical Summary
The Quanta S27 project motherboard is designed for the LGA775 socket, supporting Prescott, Smithfield, and Cedar Mill processors. The platform is built around the Mukilteo MCH northbridge paired with the ICH7R southbridge, connected via DMI. Memory architecture consists of un-buffered DDR-2 across four DIMM slots, supporting dual-channel configurations up to 8GB. The system utilizes a FWH BIOS for firmware storage. The Super I/O and EC/KBC functions are handled by the NS PC8374K. Networking is provided by dual BCM5721J LAN controllers. Graphics are driven by an XG20 VGA controller. Clock generation is managed by the ICS954201 CK410 clock generator. System management is handled by a BMC_H8 controller with dedicated SRAM, flash, and temperature sensor, alongside a BMC CPLD. Power regulation includes a CPU Voltage Regulator compliant with VRD 10.1 and a dedicated DRAM Voltage Regulator.
Technician FAQ
Q: What is the project code and board number for this motherboard?
A: The project code is S27, manufactured by Quanta Computer INC.
Q: What CPU socket and platform does this motherboard support?
A: It supports the LGA775 socket for Prescott, Smithfield, and Cedar Mill processors.
Q: What type of BIOS is used on this motherboard?
A: The motherboard uses a FWH BIOS for firmware storage.
Q: What is the memory architecture of this motherboard?
A: It supports un-buffered DDR-2 memory in a dual-channel configuration across four DIMM slots, with a maximum capacity of 8GB.
Q: What EC/KBC and Super I/O controller is used?
A: The NS PC8374K serves as both
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Quanta Computer Inc. |
| Project Code | S73 PCI_BASE |
| Document Number | C8 |
| Revision | A |
| Date | Monday, May 17, 2004 |
| EC / KBC | MEC8-80PDFHS80FR0251 |
| EC/KBC Package | 80P |
| EC Flash / ROM | AT24C02A |
Technical Summary
This Quanta Computer Inc. S73 PCI_BASE project motherboard, documented under revision A dated Monday, May 17, 2004, utilizes a MEC8-80PDFHS80FR0251 embedded controller in an 80-pin package. The EC firmware is supported by an AT24C02A serial EEPROM. The board integrates a PCI riser card slot and a SCSI gold finger connector, with power rails including P3V3, P5V, P12V, P1V5, and P3V3_STB. The design incorporates a PXA processor interface and an Intel PXH controller for PCI-X and PCI Express connectivity, with SMBus lines for system management.
Technician FAQ
Q: What EC/KBC chip is used on this motherboard?
A: The motherboard uses a MEC8-80PDFHS80FR0251 embedded controller in an 80-pin package.
Q: What EC flash/ROM device is used?
A: The EC firmware is stored on an AT24C02A serial EEPROM.
Q: What is the project code and document number for this board?
A: The project code is S73 PCI_BASE, and the document number is C8, revision A, dated May 17, 2004.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | BenQ |
| Model | DH7000 |
| Motherboard Manufacturer | BenQ |
| Project Code | 99.K1201.001 |
| Board Number | 99.K1201.002 |
| Revision | 0 |
| Document Number | 99.K1201.002-C2-201-001 |
| CPU Platform | Intel Dothan |
| PCH / Southbridge | ICH6-M (82801FM) |
| GPU Type | ATI M24P |
| EC / KBC | SMSC LPC47N249 |
| Audio Codec | ADI1980 |
| LAN IC | Realtek RTL8100CL, Realtek RTL8110SB(L) |
| WiFi / WLAN IC | Intel PRO/Wireless 2915ABG, Intel PRO/Wireless 2200BG |
| RAM Type | DDR 333 |
| RAM Quantity / Slots | 2 |
| Card Reader IC | TI PCI7411 |
Technical Summary
The BenQ DH7000 (JOYBOOK S72) motherboard, documented under project code 99.K1201.001 and board number 99.K1201.002, is built around the Intel Dothan processor platform with an Intel 915PM chipset and ICH6-M (82801FM) southbridge. Graphics are handled by an ATI M24P controller. The system uses an SMSC LPC47N249 EC/KBC and an ADI1980 audio codec. Networking is provided by Realtek RTL8100CL and RTL8110SB(L) LAN ICs, with Intel PRO/Wireless 2915ABG or 2200BG WLAN adapters. Memory configuration includes two DDR 333 slots supporting up to 2GB. The TI PCI7411 controller manages the 4-in-1 card reader.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The motherboard uses an SMSC LPC47N249 EC/KBC.
Q: What audio codec is used on this motherboard?
A: The audio codec is an ADI1980.
Q: What LAN ICs are used on this motherboard?
A: The motherboard uses Realtek RTL8100CL and Realtek RTL8110SB(L) LAN ICs.
Q: What memory type and configuration does this motherboard support?
A: The motherboard supports DDR 333 memory with 2 slots, expandable to a maximum of 2GB.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Document Number | 5544332211DDCCBBAATitleSizeDocument NumberRevDate:Sheetof<Doc><RevCode><Title>Custom11Friday, May 21, 2004BLADE_PWBTN-LH8PS_ON_PWR_NVTTENP3V3P5VVCC3_3_SUS_PGPS_PWRGDP1V5P1V5_PWRGDP1V8_DDRP1V8_PWRGDP1V2P1V2_PWRGDDelay1~5 msVID_PWRGDTo CPU0, CPU1VRD 0P_VCCP0VRD 1P_VCCP1H8_PWBTN_IN_NICH5RICH_PWRBTN_N SIO PC87373SLP_S3_NFrom CPU0, CPU1SIO_PS_ON_NVRD1_ENVRD0_ENSMC_CPU1_SKTOCC_NFrom CPU1VRD0_PWRGDVRD1_PWRGDCPU_VRD_PWRGDDelay100msSYS_PWRGD1SYS_PWRGD2PXH MCHLindenhurstTo Clock generator PCI ModuleFC DBCPU0CPU1CPU_PWR_GDICH5RPWROKVRMPWRGDDDRA_RESET_NDDRB_RESET_NDDRADDRBSLP_S5_NSMC_CPU0_SKTOCC_NFrom CPU0Delay1~5 msVRD_EN |
| Date | Friday, May 21, 2004 |
| CPU Platform | Lindenhurst |
| PCH / Southbridge | ICH5R |
| Super I/O | SIO PC87373 |
Technical Summary
This motherboard schematic, dated Friday, May 21, 2004, is built around the Lindenhurst CPU platform with an ICH5R southbridge. The system employs a dual CPU configuration (CPU0 and CPU1) with dedicated VRD controllers (VRD 0 and VRD 1) providing P_VCCP0 and P_VCCP1 power rails. Power sequencing includes VID_PWRGD, CPU_VRD_PWRGD, and SYS_PWRGD signals with specified delays. The board utilizes an SIO PC87373 Super I/O for legacy I/O management and includes SLP_S3_N and SLP_S5_N sleep state signals. Memory architecture supports DDR with separate DDR A and DDR B reset signals (DDRA_RESET_N and DDRB_RESET_N). The schematic also documents the H8_PWBTN_IN_N power button input and PS_ON_PWR_N control signals.
Technician FAQ
Q: What is the CPU platform and southbridge used on this motherboard?
A: The CPU platform is Lindenhurst and the southbridge is ICH5R.
Q: What Super I/O controller is used?
A: The Super I/O controller is SIO PC87373.
Q: What is the document date of this schematic?
A: The schematic is dated Friday, May 21, 2004.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Date | Friday, May 21, 2004 |
| PCH / Southbridge | ICH5R |
Technical Summary
This motherboard schematic, dated Friday, May 21, 2004, is built around the Intel ICH5R southbridge. The platform architecture includes CPU0 and CPU1 support, with a VGA component present. The reset and power sequencing involves signals such as SIO_PCIRST_N, SB_CPURST_N, PCI32_PCIRST_N, and RSM RST_N, with the ICH5R requiring VRMPWRGD and PWOK to be ready. The H8 EC/KBC and BIOS are also referenced in the power and reset distribution.
Technician FAQ
Q: What southbridge is used on this motherboard?
A: The Intel ICH5R southbridge is used.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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