hp pavilion dm1 flex h210-ua1 hpmh-40gab6000-c000 schematic
hp pavilion dm1=1=flex h210-ua1 hpmh-40gab6000-c000.pdf
Technical Specifications
Technical Summary
The HP H210-UA1 motherboard, revision C, is built on the Garbo-Brazos platform featuring an AMD Ontario FT1 APU in a 413-ball BGA package paired with an AMD FCH Hudson-M1 southbridge. The system memory architecture consists of two DDR3 SO-DIMM slots supporting 1/2/4 GB modules. The embedded controller is an IT8518E communicating via LPC bus. Audio is handled by an IDT 92HD80TA HDA codec. The BIOS is stored on a 16Mbit SPI ROM. Power management is managed by an ISL6265C voltage regulator, BQ24745 charger IC, and multiple power ICs including RT8209AGQW, RT8205EGQW(2), RT8015BGQW, APL5317-12BI, ME2306D-G, and ME4894-G. Networking is provided by a Realtek RTL8111E-VS-CG Gigabit LAN controller and a half-size WLAN module. Storage connectivity includes a card reader controlled by an RTS5138 IC.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The motherboard uses an IT8518E EC/KBC communicating via LPC bus.
Q: What is the BIOS flash configuration?
A: The BIOS is stored on a 16Mbit SPI ROM.
Q: What charging IC and architecture are used?
A: The charging IC is a BQ24745 configured as a charger/B+ architecture.
Q: What audio codec is present?
A: The audio codec is an IDT 92HD80TA HDA CODEC.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
hp pavilion dm1=1=flex h210-ua1 hpmh-40gab6000-c000.pdf
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | HP |
| Model | H210 |
| Motherboard Manufacturer | HPMH-40GAB6000-C000C |
| Project Code | HPMH-40GAB6000-C000C |
| Board Number | H210-UA1 Ver. C-Final-4 |
| Revision | C |
| Date | Monday, September 27, 2010 |
| CPU Platform | Garbo-Brazos Platform |
| CPU Model | Ontario FT1 |
| CPU Socket | 413 Ball BGA |
| PCH / Southbridge | AMD FCH Hudson-M1 |
| GPU Type | Integrated |
| Graphics Architecture | AMD APU |
| EC / KBC | IT8518E |
| EC/KBC Package | LPC |
| Audio Codec | IDT 92HD80TA HDA CODEC |
| BIOS / SPI Flash | SPI ROM (16Mbits) |
| BIOS Flash Capacity | 16Mbits |
| Charging IC | BQ24745 |
| Charger Architecture | Charger / B+ |
| Power IC(s) | ISL6265C, RT8209AGQW, RT8205EGQW(2), RT8015BGQW*2, APL5317-12BI, ME2306D-G, ME4894-G, G9661, G2997 |
| RAM Type | DDR3 |
| RAM Architecture | SO-DIMM |
| RAM Quantity / Slots | 2 |
| Card Reader IC | RTS5138 |
| LAN IC | Realtek RTL8111E-VS-CG |
| WiFi / WLAN IC | WLAN (HALF size) |
Technical Summary
The HP H210-UA1 motherboard, revision C, is built on the Garbo-Brazos platform featuring an AMD Ontario FT1 APU in a 413-ball BGA package paired with an AMD FCH Hudson-M1 southbridge. The system memory architecture consists of two DDR3 SO-DIMM slots supporting 1/2/4 GB modules. The embedded controller is an IT8518E communicating via LPC bus. Audio is handled by an IDT 92HD80TA HDA codec. The BIOS is stored on a 16Mbit SPI ROM. Power management is managed by an ISL6265C voltage regulator, BQ24745 charger IC, and multiple power ICs including RT8209AGQW, RT8205EGQW(2), RT8015BGQW, APL5317-12BI, ME2306D-G, and ME4894-G. Networking is provided by a Realtek RTL8111E-VS-CG Gigabit LAN controller and a half-size WLAN module. Storage connectivity includes a card reader controlled by an RTS5138 IC.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The motherboard uses an IT8518E EC/KBC communicating via LPC bus.
Q: What is the BIOS flash configuration?
A: The BIOS is stored on a 16Mbit SPI ROM.
Q: What charging IC and architecture are used?
A: The charging IC is a BQ24745 configured as a charger/B+ architecture.
Q: What audio codec is present?
A: The audio codec is an IDT 92HD80TA HDA CODEC.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Attachments
Last edited:
