hp pavilion dv4 compal la-4105p_rev1.0 schematic
hp pavilion dv4=1=compal la-4105p_rev1.0.pdf
Technical Specifications
Technical Summary
This Compal LA4105P Rev 1.0 schematic, dated 2009-07-15, details the Montevina Blade UMA platform. The core logic is built around a Mobile Penryn uFCPGA-478 CPU paired with an Intel Cantiga MCH and an Intel ICH9-M Southbridge. Graphics are integrated UMA via the Cantiga MCH. The system firmware is stored on an SST25VF080MDC SPI ROM in an SOIC-8 package. Embedded controller functions are handled by a KB926 EC/KBC. Audio is managed by an IDT9271B7 codec with a TPA6017A2 amplifier. Networking is provided by a Realtek RTL8103EL 10/100M LAN controller. The board supports dual-channel DDR3 memory via two SO-DIMM slots. A JMB385 card reader controller and an EMC1402 thermal sensor are also present. The clocking solution is an SLG8SP553V generator.
Technician FAQ
Q: What is the exact BIOS flash IC model used on this motherboard?
A: The BIOS flash IC is an SST25VF080MDC, an 8 Mbit SPI ROM in an SOIC-8 package.
Q: What EC/KBC is used on this Compal LA4105P?
A: The embedded controller is a KB926.
Q: What is the memory architecture of this motherboard?
A: The board supports dual-channel DDR3 memory via two SO-DIMM slots.
Q: What LAN controller is used on this board?
A: The LAN controller is a Realtek RTL8103EL, supporting 10/
hp pavilion dv4=1=compal la-4105p_rev1.0.pdf
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Compal |
| Motherboard Manufacturer | Compal Electronics, Inc. |
| Project Code | Montevina Blade UMA LA4105P 1.0 |
| Board Number | LA4105P |
| Revision | 1.0 |
| Date | 2009-07-15 |
| CPU Platform | Mobile Penryn uFCPGA with Intel Cantiga_GM+ICH9-M core logic |
| CPU Model | Mobile Penryn uFCPGA-478 CPU |
| CPU Socket | uFCPGA-478 |
| PCH / Southbridge | Intel ICH9-M |
| GPU Type | UMA |
| Graphics Architecture | Intel Cantiga MCH |
| EC / KBC | KB926 |
| Audio Codec | IDT9271B7 |
| BIOS / SPI Flash | SST25VF080MDC |
| BIOS Flash Exact Model | SST25VF080MDC |
| BIOS Flash Manufacturer | SST |
| BIOS Flash Capacity | 8 Mbit |
| BIOS Flash Package | SOIC-8 |
| Charging IC | Not explicitly present in source |
| RAM Type | DDR3 |
| RAM Architecture | Dual Channel |
| RAM Quantity / Slots | 2 |
| Thermal Sensor | EMC1402 |
| Card Reader IC | JMB385 |
| LAN IC | RTL8103EL |
| WiFi / WLAN IC | Not explicitly present in source |
| HDMI Level Shifter | Not explicitly present in source |
| Audio Amplifier | TPA6017A2 |
| Clock Generator | SLG8SP553V |
| SPI ROM | SST25VF080MDC |
Technical Summary
This Compal LA4105P Rev 1.0 schematic, dated 2009-07-15, details the Montevina Blade UMA platform. The core logic is built around a Mobile Penryn uFCPGA-478 CPU paired with an Intel Cantiga MCH and an Intel ICH9-M Southbridge. Graphics are integrated UMA via the Cantiga MCH. The system firmware is stored on an SST25VF080MDC SPI ROM in an SOIC-8 package. Embedded controller functions are handled by a KB926 EC/KBC. Audio is managed by an IDT9271B7 codec with a TPA6017A2 amplifier. Networking is provided by a Realtek RTL8103EL 10/100M LAN controller. The board supports dual-channel DDR3 memory via two SO-DIMM slots. A JMB385 card reader controller and an EMC1402 thermal sensor are also present. The clocking solution is an SLG8SP553V generator.
Technician FAQ
Q: What is the exact BIOS flash IC model used on this motherboard?
A: The BIOS flash IC is an SST25VF080MDC, an 8 Mbit SPI ROM in an SOIC-8 package.
Q: What EC/KBC is used on this Compal LA4105P?
A: The embedded controller is a KB926.
Q: What is the memory architecture of this motherboard?
A: The board supports dual-channel DDR3 memory via two SO-DIMM slots.
Q: What LAN controller is used on this board?
A: The LAN controller is a Realtek RTL8103EL, supporting 10/
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