hp pavilion dv4 cq41 compal la-4106p_rev1.0 schematic
hp pavilion dv4 cq41=1=compal la-4106p_rev1.0.pdf
Technical Specifications
Technical Summary
This Compal LA4106P Rev 1.0 schematic, dated November 12, 2009, documents a Mobile Arrandale rPGA989 platform with Intel PCH (Ibex Peak-M) core logic. The UMA graphics architecture is paired with dual-channel DDR3 1066 1.5V memory across two SO-DIMM slots. The EC/KBC is a KB926 controller with 256K Bytes of EC flash. The BIOS subsystem utilizes two SPI ROMs: a 2M MX25L2005CMI-12G and a 32M AT25DF321-SU. Audio is handled by an IDT92HD80 codec, while networking and card reader functions are integrated into a single RTL8401 IC. The clocking solution is an ICS9LRS3197AKLFT MLFP19 (CK505) generator.
Technician FAQ
Q: What BIOS IC models are used on this motherboard?
A: This motherboard uses two SPI ROMs: a 2M MX25L2005CMI-12G and a 32M AT25DF321-SU.
Q: What EC/KBC controller is used on this motherboard?
A: The EC/KBC controller is a KB926 with 256K Bytes of EC flash.
Q: What is the memory architecture of this motherboard?
A: The memory architecture is dual-channel DDR3 1066 1.5V, using two DDR3 SO-DIMM slots.
Q: What is the graphics architecture of this motherboard?
A: The graphics architecture is UMA (Unified Memory Architecture).
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
hp pavilion dv4 cq41=1=compal la-4106p_rev1.0.pdf
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Compal |
| Motherboard Manufacturer | Compal Electronics, Inc. |
| Project Code | Calpella_UMA_LA4106P |
| Board Number | LA4106P |
| Revision | 1.0 |
| Date | Thursday, November 12, 2009 |
| CPU Platform | Mobile Arrandale rPGA989 with Intel PCH(Ibex Peak-M) core logic |
| CPU Socket | Socket-rPGA989 |
| PCH / Southbridge | Intel PCH (Ibex Peak-M) |
| Graphics Architecture | UMA |
| EC / KBC | KB926 |
| Audio Codec | IDT92HD80 |
| BIOS / SPI Flash | SPI ROM 2M (MX25L2005CMI-12G) + SPI ROM 32M (AT25DF321-SU) |
| BIOS Flash Capacity | 2M + 32M |
| EC Flash / ROM | 256K Bytes |
| RAM Type | DDR3 1066 1.5V |
| RAM Architecture | Dual Channel |
| RAM Quantity / Slots | DDR3 SO-DIMM X2 |
| LAN IC | RTL8401 (LAN+Card reader) |
| Card Reader IC | RTL8401 (LAN+Card reader) |
| Clock Generator | ICS9LRS3197AKLFT MLFP19 (CK505) |
| Document Number | Custom145 |
Technical Summary
This Compal LA4106P Rev 1.0 schematic, dated November 12, 2009, documents a Mobile Arrandale rPGA989 platform with Intel PCH (Ibex Peak-M) core logic. The UMA graphics architecture is paired with dual-channel DDR3 1066 1.5V memory across two SO-DIMM slots. The EC/KBC is a KB926 controller with 256K Bytes of EC flash. The BIOS subsystem utilizes two SPI ROMs: a 2M MX25L2005CMI-12G and a 32M AT25DF321-SU. Audio is handled by an IDT92HD80 codec, while networking and card reader functions are integrated into a single RTL8401 IC. The clocking solution is an ICS9LRS3197AKLFT MLFP19 (CK505) generator.
Technician FAQ
Q: What BIOS IC models are used on this motherboard?
A: This motherboard uses two SPI ROMs: a 2M MX25L2005CMI-12G and a 32M AT25DF321-SU.
Q: What EC/KBC controller is used on this motherboard?
A: The EC/KBC controller is a KB926 with 256K Bytes of EC flash.
Q: What is the memory architecture of this motherboard?
A: The memory architecture is dual-channel DDR3 1066 1.5V, using two DDR3 SO-DIMM slots.
Q: What is the graphics architecture of this motherboard?
A: The graphics architecture is UMA (Unified Memory Architecture).
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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