toshiba nb520 la-6858p rev 1.0
Technical Specifications
Technical Summary
This Compal LA-6858P REV:1.0 schematic, designated under Project Code QBU00, details the Cougar 2.0 platform built around an Intel Cedar Trail processor (Intel Cedarview 2 Core 1.86GHz) paired with the Tiger Point PCH. The system memory architecture is based on a single 204-pin DDRIII-SO-DIMM slot supporting 1.5V DDRIII 1066MHz modules. The main BIOS is stored on a 2MB SPI ROM, while the ENE KB930 E0 embedded controller utilizes a separate 128KB SPI ROM for its firmware. Integrated audio is handled by the ALC269 HDA codec, and networking is provided by the RTL8105E 10/100 LAN controller. A dedicated RTL5137 IC manages the integrated card reader interface.
Technician FAQ
Q: What is the board number and project code for this motherboard?
A: The board number is LA-6858P REV:1.0, and the project code is QBU00.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is an ENE KB930 E0.
Q: What are the BIOS and EC flash configurations?
A: The main BIOS is stored on a 2MB SPI ROM, and the EC firmware is stored on a separate 128KB SPI ROM.
Q: What is the CPU and PCH platform?
A: The CPU is an Intel Cedarview 2 Core 1.86GHz (6.5W) from the Cedar Trail family, paired with the Tiger Point PCH.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Compal |
| Motherboard Manufacturer | Compal Electronics, Inc. |
| Project Code | QBU00 |
| Board Number | LA-6858P |
| Revision | REV:1.0 |
| Date | 2011-11-07 |
| Document Number | 4019EHBSCH |
| CPU Platform | Intel Cedar Trail |
| CPU Model | Intel Cedarview 2 Core 1.86GHz (6.5W) |
| PCH / Southbridge | Tiger Point |
| EC / KBC | ENE KB930 E0 |
| Audio Codec | ALC269 |
| BIOS / SPI Flash | SPI ROM 2MB |
| BIOS Flash Capacity | 2MB |
| EC Flash / ROM | SPI ROM 128KB |
| RAM Type | DDRIII |
| RAM Architecture | 204pin DDRIII-SO-DIMM |
| RAM Quantity / Slots | 1.5V DDRIII 1066MHz |
| LAN IC | RTL8105E 10/100 LAN |
| Card Reader IC | RTL5137 |
| WiFi / WLAN IC | PCIeMini Card WLAN +BT COMBO |
Technical Summary
This Compal LA-6858P REV:1.0 schematic, designated under Project Code QBU00, details the Cougar 2.0 platform built around an Intel Cedar Trail processor (Intel Cedarview 2 Core 1.86GHz) paired with the Tiger Point PCH. The system memory architecture is based on a single 204-pin DDRIII-SO-DIMM slot supporting 1.5V DDRIII 1066MHz modules. The main BIOS is stored on a 2MB SPI ROM, while the ENE KB930 E0 embedded controller utilizes a separate 128KB SPI ROM for its firmware. Integrated audio is handled by the ALC269 HDA codec, and networking is provided by the RTL8105E 10/100 LAN controller. A dedicated RTL5137 IC manages the integrated card reader interface.
Technician FAQ
Q: What is the board number and project code for this motherboard?
A: The board number is LA-6858P REV:1.0, and the project code is QBU00.
Q: What EC/KBC is used on this motherboard?
A: The embedded controller is an ENE KB930 E0.
Q: What are the BIOS and EC flash configurations?
A: The main BIOS is stored on a 2MB SPI ROM, and the EC firmware is stored on a separate 128KB SPI ROM.
Q: What is the CPU and PCH platform?
A: The CPU is an Intel Cedarview 2 Core 1.86GHz (6.5W) from the Cedar Trail family, paired with the Tiger Point PCH.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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