toshiba nb520 la-6859p rev 1.0
Technical Specifications
Technical Summary
This Compal LA-6859P Rev 1.0 schematic, dated 2011-11-07, documents the Cougar 2.0 platform based on an Intel Cedar Trail Processor (Cedarview 2 Core 1.86GHz) paired with a Tiger Pointer PCH. The system utilizes an ENE KB930 E0 EC/KBC with a dedicated 128KB SPI ROM. The main BIOS is stored on a 2MB SPI ROM. Memory architecture consists of a single 204-pin DDRIII SO-DIMM slot supporting 1.5V DDRIII 1066MHz. Integrated audio is handled by an ALC269 HDA codec, while networking is provided by an RTL8105E 10/100 LAN controller. A Realtek RTL5137 card reader IC and an RTM890N-397 low power clock generator are also present on the board.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The motherboard uses an ENE KB930 E0 EC/KBC with a dedicated 128KB SPI ROM.
Q: What is the BIOS flash configuration?
A: The main BIOS is stored on a 2MB SPI ROM.
Q: What is the memory architecture?
A: The board supports a single 204-pin DDRIII SO-DIMM module running at 1.5V DDRIII 1066MHz.
Q: What LAN and audio controllers are used?
A: The LAN controller is a Realtek RTL8105E 10/100, and the audio codec is a Realtek ALC269.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | Compal |
| Motherboard Manufacturer | Compal Electronics, Inc. |
| Project Code | QBU00 |
| Board Number | LA-6859P |
| Revision | 1.0 |
| Date | 2011-11-07 |
| CPU Platform | Intel Cedar Trail Processor / Tiger point |
| Platform Alias | Cougar 2.0 |
| CPU Model | Intel Cedarview 2 Core 1.86GHz (6.5W) |
| PCH / Southbridge | Tiger Pointer |
| EC / KBC | ENE KB930 E0 |
| Audio Codec | ALC269 |
| BIOS / SPI Flash | SPI ROM 2MB |
| EC Flash / ROM | SPI ROM 128KB |
| RAM Type | DDRIII-SO-DIMM |
| RAM Architecture | 1.5V DDRIII 1066MHz |
| LAN IC | RTL8105E 10/100 LAN |
| Card Reader IC | RTL5137 |
| Clock Generator | RTM890N-397 |
Technical Summary
This Compal LA-6859P Rev 1.0 schematic, dated 2011-11-07, documents the Cougar 2.0 platform based on an Intel Cedar Trail Processor (Cedarview 2 Core 1.86GHz) paired with a Tiger Pointer PCH. The system utilizes an ENE KB930 E0 EC/KBC with a dedicated 128KB SPI ROM. The main BIOS is stored on a 2MB SPI ROM. Memory architecture consists of a single 204-pin DDRIII SO-DIMM slot supporting 1.5V DDRIII 1066MHz. Integrated audio is handled by an ALC269 HDA codec, while networking is provided by an RTL8105E 10/100 LAN controller. A Realtek RTL5137 card reader IC and an RTM890N-397 low power clock generator are also present on the board.
Technician FAQ
Q: What EC/KBC is used on this motherboard?
A: The motherboard uses an ENE KB930 E0 EC/KBC with a dedicated 128KB SPI ROM.
Q: What is the BIOS flash configuration?
A: The main BIOS is stored on a 2MB SPI ROM.
Q: What is the memory architecture?
A: The board supports a single 204-pin DDRIII SO-DIMM module running at 1.5V DDRIII 1066MHz.
Q: What LAN and audio controllers are used?
A: The LAN controller is a Realtek RTL8105E 10/100, and the audio codec is a Realtek ALC269.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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